Mac - Intel 460GX Software Developer’s Manual

This register records and latches the data corresponding to the first DED detected by system bus
interface in the SDC.
Bits
63:0
2.4.2.30 DEDF_ECC_FERR: ECC on First System Bus DED
Bus CBN, Device Number:
Address Offset:
Default Value:
This register records and latches the ECC checkbits corresponding to the first DED detected by
system bus interface in the SDC.
Bits
7:0
2.4.2.31 DEDF_TXINFO_FERR: TXINFO on First System Bus DED
Bus CBN, Device Number:
Address Offset:
Default Value:
This register records the ITID and failing chunk corresponding to the first DED detected by system
bus interface in the SDC.
Bits
15:9
8:6
5:0
2.4.3

MAC

2.4.3.1 FERR_MAC: First Error Status Register
Bus CBN, Device Number: 05h,06h
Address Offset:
Default Value:
This register records the first error condition detected in the MAC.
Bits
7:2
1
Intel® 460GX Chipset Software Developer's Manual
Description
DE - System Data of Error.
04h
F8h
00h
Description
ECC - ECC of Error.
04h
F9-FAh
00h
Description
reserved(0)
DC - Data Chunk of ITID.
ITID - ITID of error.
98h
00h
Description
reserved(0)
Que-Overflow Error
Signals that the MAC received too many commands from the SAC.
Size: 8 bits
Attribute: Read Only, New Value Latched
anytime appropriate FERR register
bit is set
Size: 16 bits
Attribute: Read Only, New Value Latched
anytime appropriate FERR register
bit is set
Function Number: 00h,01h
Size:
Attribute:
Register Descriptions
8 bits
Read
2-21