Intel 460GX Software Developer’s Manual page 37

This register records and latches the data associated with the first parity error detected on the
PITID bus.
Bits
7
6
5:0
2.4.2.17 SDCRSP_FERR: Response on First SDCRSP Error
Bus CBN, Device Number:
Address Offset:
Default Value:
This register records and latches the data and inverted data associated with the first transmission
error detected on the SDCRSP bus.
Bits
7:4
3:0
2.4.2.18 DPBRLE_FERR: Private Data Bus Receive Length Error
Bus CBN, Device Number:
Address Offset:
Default Value:
This register indicates that the amount of data transferred from the SAC to the SDC for a given
transfer did not match the expected transfer length.
Bits
7:3
2
1
0
2.4.2.19 ECCMSK0: ECC Mask Register - Card B
Bus CBN, Device Number:
Address Offset:
Default Value:
This register is used to test the ECC error detection logic in the memory subsystem for memory
card 0. To test, this register is written with a masking function. All subsequent writes into memory
will store a masked version of the computed ECC. Subsequent reads of memory locations written
Intel® 460GX Chipset Software Developer's Manual
Description
If set then the error was detected on the 1
these fields contain the information from the 2
Parity of Error
PITID - Private ITID bus value of Error.
04h
8Dh
0h
Description
nd
Response Bus for 2 half of double–pumped transfer.
st
Response Bus for 1 half of double–pumped transfer.
04h
8Eh
0h
Description
reserved(0)
Data packet longer than expected (LDP)
Data packet shorter than expected (SDP)
No data packet shipped as expected (NDP)
04h
C8h
00h
st
half of the double-pumped transfer. Otherwise,
nd
half of the double-pumped transfer.
Size: 8 bits
Attribute: Read Only, New Value Latched
anytime appropriate FERR register
bit is set
Size: 8 bits
Attribute: Read Only, New Value Latched
anytime appropriate FERR register
bit is set
Size: 8 bits
Attribute: Read/Write
Register Descriptions
2-17