Intel 460GX Software Developer’s Manual page 45

Default Value:
Sticky:
These registers record and latch the first error detected in the AGP interface.
Bits
7:6
5
4
3
2
1
0
2.4.5.4 FERR_GART: First Error Status Register for GART
Function Number:
Address Offset:
Default Value:
Sticky:
These registers record and latch the first error detected in the AGP interface.
Bits
7:4
3
2
1
0
2.4.5.5 NERR_AGP: Next Errors Status Register for AGP
Function Number:
Address Offset:
Default Value:
Sticky:
This register records all error conditions detected in the AGP interface after the first error. Errors
recorded in FERR_AGP are not recorded here.
Bits
7:0
Intel® 460GX Chipset Software Developer's Manual
00h
Yes
Description
reserved (0)
Lo-priority Read Data Que Parity Error
This is data returned to the graphics card out of the Low-priority buffer.
Hi-priority Read Data Que Parity Error
This is data returned to the graphics card out of the Hi-priority buffer.
Use of Pipe with Sideband Enabled
AGP address from graphics card [63:40] not equal to 0
AGP Request Queue Overflow
The GXB supports 16 outstanding requests. This bit is set if a new request is sent by the
AGP card when the GXB already has 16 requests.
Illegal AGP Command
BFN+1
86h
00h
Yes
Description
reserved (0)
GART Parity Error.
GART Entry Invalid
Illegal Address (after GART translation) in range between GAPBAS and GAPTOP, or
in VGA range and VGAGE is asserted, or directed by MARG to PCI instead of memory,
or above TOM.
reserved (0)
BFN+1
8Dh
00h
Yes
Description
See FERR_AGP for definition of these bits.
Register Descriptions
Attribute: Read/Write Clear
Locked: No
Size: 8 bits
Attribute: Read/Write Clear
Locked: No
Size: 8 bits
Attribute: Read/Write Clear
Locked: No
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