Intel 460GX Software Developer’s Manual page 166

IFB Register Mapping
Table 9-1. PCI Configuration Registers–Function 0(PCI to LPC/FWH Interface Bridge)
(Cont'd)
Configuration Offset
06–07h
08h
09-0Bh
0C–0Dh
0Eh
0F–3Fh
40–43h
44h
45h
46–4Bh
4Ch
4Dh
4E–4Fh
50–5Fh
60–63h
64h
65–68h
69h
6A–6Bh
6C–75h
76–77h
78–7Bh
7C–7Fh
80h
81h
82h
83h
84–85h
86–8Fh
90-91h
92-95h
96-C7h
C8h
C9–CFh
D0–D3h
D4h
D5–DFh
E0h
E1h
E2h
E3h
E4–E5h
E6–E7h
E8h
E9–FFh
9-2
Mnemonic
PCISTS PCI Device Status
RID Revision Identification
CLASSC Class Code
– Reserved
HEDT Header Type
– Reserved
ACPIBR ACPI Base Address Register
ACPIEN ACPI Enable
SCIRC Reserved
– Reserved
– Reserved
– Reserved
BIOSEN Reserved
– Reserved
PIRQRC[A:D] Reserved
SERIRQC Serial IRQ Control
– Reserved
TOM Top of Memory
MSTAT Miscellaneous Status
– Reserved
– Reserved
– Reserved
– Reserved
– APIC Base Address Relocation
– Reserved
DLC Deterministic Latency Control
– Reserved
MGPIOC Muxed GPIO Control
– Reserved
PDMACFG PCI DMA Configuration
DDMABASE Distributed DMA Slave Base Pointer
– Reserved
RTCCFG Real Time Clock Configuration
– Reserved
GPIOBA GPIO Base Address Register
GPIOE GPIO Enable
– Reserved
LPCCD LPC COM Decode
LPCFD LPC FDD/LPT Decode
LPCSD LPC Sound Decode
FWHDE Firmware Hub Decode Enable
LPCGD LPC Generic Decode Range
LPCDE LPC Decode Enables
FWHS Firmware Hub Select
– Reserved
Intel® 460GX Chipset Software Developer's Manual
Register Register Access
R/W
RO
RO
–
RO
–
R/W
R/W
R/W
–
R/W
–
R/W
–
R/W
R/W
–
R/W
R/W
–
R/W
R/W
–
R/W
–
R/W
–
R/W
–
R/W
R/W
–
R/W
–
R/W
R/W
–
R/W
R/W
R/W
–
R/W
R/W
–
–