Table 9-24. Ide Register Transfer To/From Device Timing Parameters - AMD Geode SC3200 Data Book

Electrical Specifications

Table 9-24. IDE Register Transfer to/from Device Timing Parameters

Symbol Parameter
t Cycle time (min)
0
t Address valid to IDE_IOR[0:1]#/
1
IDE_IOW[0:1]# setup (min)
t IDE_IOR[0:1]#/IDE_IOW[0:1]# pulse
2
width 8-bit (min)
t IDE_IOR[0:1]#/IDE_IOW[0:1]#
2i
recovery time (min)
t IDE_IOW[0:1]# data setup (min)
3
t IDE_IOW[0:1]# data hold (min)
4
t IDE_IOR[0:1]# data setup (min)
5
t IDE_IOR[0:1]# data hold (min)
6
t IDE_IOR[0:1]# data TRI-STATE
6Z
(max)
t IDE_IOR[0:1]#/IDE_IOW[0:1]# to
9
address valid hold (min)
t Read data valid to IDE_IORDY[0:1]
RD
active (if IDE_IORDY[0:1] initially low
after t (min)
A
t IDE_IORDY[0:1] setup time
A
t IDE_IORDY[0:1] pulse width (max)
B
t IDE_IORDY[0:1] assertion to release
C
(max)
Note 1. t is the minimum total cycle time, t
0
ery time or command inactive time. The actual cycle time equals the sum of the command active time and the com-
mand inactive time. The three timing requirements of t
requirements is greater than the sum of t
t to ensure that t
2i
Note 2. This parameter specifies the time from the rising edge of IDE_IOR[0:1]# to the time that the data bus is no longer
driven by the device (TRI-STATE).
Note 3. The delay from the activation of IDE_IOR[0:1]# or IDE_IOW[0:1]# until the state of IDE_IORDY[0,1] is first sampled.
If IDE_IORDY[0:1] is inactive, then the host waits until IDE_IORDY[0:1] is active before the PIO cycle is completed.
If the device is not driving IDE_IORDY[0:1] negated after activation (t
t is met and t is not applicable. If the device is driving IDE_IORDY[0:1] negated after activation (t
5 RD
IDE_IOR[0:1]# or IDE_IOW[0:1]#, then t
AMD Geode™ SC3200 Processor Data Book
1250
is the minimum command active time, and t
2
and t
2
is equal to or greater than the value reported in the device's IDENTIFY DEVICE data.)
0
is met and t
RD
Mode
0 1 2
600 383 240
70 50 30
290 290 290
- - -
60 45 30
30 20 15
50 35 20
5 5 5
30 30 30
20 15 10
0 0 0
35 35 35
1250 1250 1250
5 5 5
, t , and t are met. The minimum total cycle time
0 2 2i
. (This means that a host implementation can lengthen t
2i
) of IDE_IOR[0:1]# or IDE_IOW[0:1]#, then
A
is not applicable.
5
32581C
3 5 Unit Comments
180 120 ns Note 1
30 25 ns
80 70 ns Note 1
70 25 ns Note 1
30 20 ns
10 10 ns
20 20 ns
5 5 ns
30 30 ns Note 2
10 10 ns
0 0 ns
35 35 ns Note 3
1250 ns
5 5 ns
is the minimum command recov-
2i
and/or
2
) of
A
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