AMD Geode SC3200 Data Book page 72

32581C
Table 4-2. Multiplexing, Interrupt Selection, and Base Address Registers (Continued)
Bit Description
23 TFTPP (TFT/Parallel Port). Determines whether certain balls are used for TFT or PP/ACB1/FPCI. This bit is set to 1 at
power-on if the TFT_PRSNT strap (ball P29) is pulled high.
Ball #
H2 / D10
H3 / A9
J4 / A10
T1 / B17
T3 / D17
T4 / C17
U1 / A18
U3 / B18
V1 / C18
V2 / C19
V3 / A20
W1 / B20
W2 / C20
W3 / D20
Y1 / A21
Y3 / B21
AA1 / C21
AA3 / D21
AB1 / A22
AB2 / D22
AJ13 / N31
AL12 / N30
AL16 / V30
Note: 1. PMR[27] = 0 and FPCI_MON = 0
2. PMR[27] = 1 or FPCI_MON = 1
3. ACCESS.bus interface 1 is not available if PMR[23] = 1.
4. If FPCI_MON strap is enabled, the TFT_PRSNT strap should pulled low.
22 RSVD (Reserved). Must be set equal to PMR[14] (LPCSEL). The LPC_ROM strap (ball D6) determines the power-on reset
(POR) state of PMR[14] and PMR[22].
72
0: PP/ACB1/FPCI
Name Add'l Dependencies
GPIO1 PMR[13] = 0
IOCS1# PMR[13] = 1
GPIO20 PMR[7] = 0
DOCCS# PMR[7] = 1
GPIO17 PMR[5] = 0
IOCS0# PMR[5] = 1
BUSY/WAIT# Note 1
F_C/BE1# Note 2
PE Note 1
F_C/BE2# Note 2
SLCT Note 1
F_C/BE3# Note 2
PD7 Note 1
F_AD7 Note 2
ACK# Note 1
FPCICLK Note 2
PD4 Note 1
F_AD4 Note 2
PD5 Note 1
F_AD5 Note 2
PD6 Note 1
F_AD6 Note 2
SLIN#/ASTRB# Note 1
F_IRDY# Note 2
PD3 Note 1
F_AD3 Note 2
PD2 Note 1
F_AD2 Note 2
PD1 Note 1
F_AD1 Note 2
INIT# Note 1
SMI_O Note 2
PD0 Note 1
F_AD0 Note 2
ERR# Note 1
F_C/BE0# Note 2
STB#/WRITE# Note 1
F_FRAME# Note 2
AFD#/DSTRB# Note 1
INTR_O Note 2
AB1C None
AB1D None
GXCLK PMR[29] = 0
TEST3 PMR[29] = 1
General Configuration Block
1: TFT
Name Add'l Dependencies
TFTD12 None
TFTD0 None
TFTDCK None
TFTD3 None
TFTD14 Note 1
TFTD15 Note 1
TFTD13 Note 1
TFTDE Note 1
TFTD10 Note 1
TFTD11 Note 1
TFTD1 Note 1
TFTD16 Note 1
TFTD9 Note 1
TFTD8 Note 1
TFTD7 Note 1
TFTD5 Note 1
TFTD6 Note 1
TFTD4 Note 1
TFTD17 None
TFTD2 Note 1
GPIO20 PMR[7] = 0
DOCCS# PMR[7] = 1
GPIO1 PMR[13] = 0
IOCS1# PMR[13] = 1
FP_VDD_ON None
AMD Geode™ SC3200 Processor Data Book