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Signal Definitions
3.4.7
Sub-ISA Interface Signals
Signal Name
Ball No.
A[23:0]
See Table
3-3 on
page 40.
D15
See Table
3-3 on
D14
page 40.
D13
D12
D11
D10
D9
D8
D[7:0]
BHE#
IOCS1#
D10
N30
IOCS0#
A10
ROMCS#
C30
DOCCS#
N31
TRDE#
D11
RD#
WR#
IOR#
IOW#
DOCR#
DOCW#
IRQ9
AA3
IOCHRDY
AMD Geode™ SC3200 Processor Data Book
Type
Description
O
Address Lines
I/O
Data Bus
E4
O
Byte High Enable. With A0, defines byte
accessed for 16 bit wide bus cycles.
O
I/O Chip Selects
O
ROM or Flash ROM Chip Select
A9
O
DiskOnChip or NAND Flash Chip Select
O
Transceiver Data Enable Control. Active low for
Sub-ISA data transfers. The signal timing is as fol-
lows:
• In a read cycle, TRDE# has the same timing as
RD#.
• In a write cycle, TRDE# is asserted (to active
low) at the time WR# is asserted. It continues
being asserted for one PCI clock cycle after
WR# has been negated, then it is negated.
B8
O
Memory or I/O Read. Active on any read cycle.
B9
O
Memory or I/O Write. Active on any write cycle.
D9
O
I/O Read. Active on any I/O read cycle.
A8
O
I/O Write. Active on any I/O write cycle.
D9
O
DiskOnChip or NAND Flash Read. Active on any
memory read cycle to DiskOnChip.
A8
O
DiskOnChip or NAND Flash Write. Active on
any memory write cycle to DiskOnChip.
I
Interrupt 9 Request Input. Active high.
Note: If IRQ9 function is selected but not used,
C9
I
I/O Channel Ready
Note: If IOCHRDY function is selected but not
tie IRQ9 low.
used, tie IOCHRDY high.
32581C
Mux
AD[23:0]
STOP#
IRDY#
TRDY#
PAR
C/BE3#
C/BE2#
C/BE1#
C/BE0#
AD[31:24]
DEVSEL#
GPIO1+TFTD12
AB1D+GPIO1
GPIO17+TFTDCK
BOOT16 (Strap)
GPIO20+TFTD0
AB1C+GPIO20
GPIO0
CLKSEL0 (Strap)
---
DOCR#+GPIO14
DOCW#+GPIO15
IOR#+GPIO14
IOW#+GPIO15
IDE_DATA6
GPIO19+INTC#
57
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