Table 9-12. Memory Controller Timing Parameters - AMD Geode SC3200 Data Book

32581C
Symbol Parameter
t Control output valid from SDCLK[3:0]
1
t MA[12:0], BA[1.0] output valid from
2
SDCLK[3:0]
t MD[63.0] output valid from SDCLK[3:0]
3
t MD[63.0] read data in setup to SDCLK_IN
4
t MD[63:0] read data hold to SDCLK_IN
5
t SDCLK[3:0], SDCLK_OUT cycle time
6
233 MHz
266 MHz
t SDCLK[3:0], SDCLK_OUT fall/rise time
7
between (V
OLD
t SDCLK_IN fall/rise time between
9
(V -V )
ILD IHD
t SDCLK[3:0], SDCLK_OUT high time
10
233 MHz
266 MHz
t SDCLK[3:0], SDCLK_OUT low time
11
233 MHz
266 MHz
Note 1. Control output includes all the following signals: RASA#, CASA#, WEA#, CKEA, DQM[7:0], and CS[1:0]#.
Load = 50 pF, V
CORE
Note 2. Use the Min/Max equations [value+(x * y)] to calculate the actual output value.
x is the shift value which is applied to the SHFTSDCLK field, and y is 0.45 the core clock period.
Note that the SHFTSDCLK field = GX_BASE+Memory Offset 8404h[5:3]. Refer to the AMD Geode™ GX1 Proces-
sor Data Book for more information.
For example, for a 266 MHz SC3200 running a 88.7 MHz SDRAM clock, with a shift value of 3:
t1 Min = -3 + (3 * (3.76 * 0.45)) = 2.08 ns
t1 Max = 0.1 + (3 * (3.76 * 0.45)) = 5.18 ns
364

Table 9-12. Memory Controller Timing Parameters

-V )
OHD
= 1.8V@ 233/266 MHz, V
Min Max
-3.0 + (x y) 0.1 + (x
*
-3.2 + (x y) 0.1 + (x
*
-2.2 + (x y) 0.7 + (x
*
1.3
2.0
10 14
8.3 13.5
2
2
4.0
3.0
4.0
2.5
o
= 3.3V, @25 C.
IO
AMD Geode™ SC3200 Processor Data Book
Electrical Specifications
Unit Comments
y) ns Note 1, Note 2
*
y) ns Note 2
*
y) ns Note 2
*
ns
ns
ns
ns
ns
ns
ns