Table 5-47. Bank Selection Encoding; Table 5-48. Bank 1 Register Map; Table 5-49. Bank 2 Register Map - AMD Geode SC3200 Data Book

32581C
7 6 5
0 x x
1 0 x
1 1 x
1 1 x
1 1 1
1 1 1
1 1 1
1 1 1
1 1 1
1 1 1
Offset Type
00h R/W
01h R/W
02h ---
03h W
R/W
04h-07h ---
1. When bit 7 of this register is set to 1, bits [6:0] of BSR select the bank, as shown in Table 5-47.
Offset Type
00h R/W
01h R/W
02h R/W
03h R/W
04h R/W
05h ---
06h RO
07h RO
134

Table 5-47. Bank Selection Encoding

BSR Bits
4 3 2
x x x
x x x
x x x
x x x
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1

Table 5-48. Bank 1 Register Map

Name
LBGD(L). Legacy Baud Generator Divisor Port (Low Byte)
LBGD(H). Legacy Baud Generator Divisor Port (High Byte)
RSVD. Reserved
1
LCR . Link Control
1
BSR . Bank Select
RSVD. Reserved

Table 5-49. Bank 2 Register Map

Name
BGD(L). Baud Generator Divisor Port (Low Byte)
BGD(H). Baud Generator Divisor Port (High Byte)
EXCR1. Extended Control 1
BSR. Bank Select
EXCR2. Extended Control 2
RSVD. Reserved
TXFLV. TX FIFO Level
RXFLV. RX FIFO Level
1 0 Bank Selected
x x 0
x x 1
1 x 1
x 1 1
0 0 2
0 0 3
0 0 4
0 0 5
0 0 6
0 0 7
AMD Geode™ SC3200 Processor Data Book
SuperI/O Module
Functionality
UART + IR
IR Only