Table 5-13. Relevant Acb1 And Acb2 Registers; Table 5-14. Acb1 And Acb2 Configuration Register - AMD Geode SC3200 Data Book

SuperI/O Module
5.4.2.5 LDN 05h and 06h - ACCESS.bus Ports 1 and 2
ACCESS.bus ports 1 and 2 (ACB1 and ACB2) are identi-
cal. Each ACB is a two-wire synchronous serial interface
compatible with the ACCESS.bus physical layer. ACB1 and
ACB2 use a 24 MHz internal clock. Six runtime registers for
each ACCESS.bus are
"ACCESS.bus Interface" on page 119.
Index Type Configuration Register or Action
30h R/W Activate. See also bit 0 of the SIOCF1 register
60h R/W Base Address MSB register.
61h R/W Base Address LSB register. Bits [2:0] (for A[2:0]) are RO, 000b.
70h R/W Interrupt Number.
71h R/W Interrupt Type. Bit 1 is R/W. Other bits are RO.
74h RO Report no DMA assignment.
75h RO Report no DMA assignment.
F0h R/W ACB1 and ACB2 Configuration register.
Bit Description
Index F0h
This register is reset by hardware to 00h.
7:3 Reserved.
2 Internal Pull-Up Enable.
0: No internal pull-up resistors on AB1C/AB2C and AB1D/AB2D. (Default)
1: Internal pull-up resistors on AB1C/AB2C and AB1D/AB2D.
1:0 Reserved.
AMD Geode™ SC3200 Processor Data Book
described in Section 5.7

Table 5-13. Relevant ACB1 and ACB2 Registers

Table 5-14. ACB1 and ACB2 Configuration Register

ACB1 and ACB2 Configuration Register (R/W)
ACB1 is designated as LDN 05h and ACB2 as LDN 06h.
Table 5-13 lists the configuration registers which affect the
ACCESS.bus ports. Only the last register (F0h) is
described here (Table 5-14). See Table 5-3 "Standard Con-
figuration Registers" on page 93 for descriptions of the oth-
ers.
32581C
Reset
Value
00h
00h
00h
00h
03h
04h
04h
00h
101