Table 6-39. F5: Pci Header Registers For X-Bus Expansion - AMD Geode SC3200 Data Book

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6.4.5 X-Bus Expansion Interface - Function 5
The register space designated as Function 5 (F5) is used
to configure the PCI portion of support hardware for
accessing the X-Bus Expansion support registers. The bit
formats for the PCI Header Registers are given in Table 6-
39.

Table 6-39. F5: PCI Header Registers for X-Bus Expansion

Bit Description
Index 00h-01h
Index 02h-03h
Index 04h-05h
15:2 Reserved. (Read Only)
1 Memory Space. Allow the Core Logic module to respond to memory cycles from the PCI bus.
0: Disable.
1: Enable.
If F5BAR0, F5BAR1, F5BAR2, F5BAR3, F5BAR4, and F5BAR5 (F5 Index 10h, 14h, 18h, 1Ch, 20h, and 24h) are defined as
allowing access to memory mapped registers, this bit must be set to 1. BAR configuration is programmed through the corre-
sponding mask register (see F5 Index 40h, 44h, 48h, 4Ch, 50h, and 54h)
0 I/O Space. Allow the Core Logic module to respond to I/O cycle from the PCI bus.
0: Disable.
1: Enable.
If F5BAR0, F5BAR1, F5BAR2, F5BAR3, F5BAR4, and F5BAR5 (F5 Index 10h, 14h, 18h, 1Ch, 20h, and 24h) are defined as
allowing access to I/O mapped registers, this bit must be set to 1. BAR configuration is programmed through the corre-
sponding mask register (see F5 Index 40h, 44h, 48h, 4Ch, 50h, and 54h)
Index 06h-07h
Index 08h
Index 09h-0Bh
Index 0Ch
Index 0Dh
Index 0Eh
Index 0Fh
Index 10h-13h
X-Bus Expansion Address Space. This register allows PCI access to I/O mapped X-Bus Expansion support registers. Bits [5:0] must
be set to 000001, indicating a 64-byte aligned I/O address space. Refer to Table 6-40 on page 280 for the X-Bus Expansion configura-
tion register bit formats and reset values.
Note: The size and type of accessed offsets can be reprogrammed through F5BAR0 Mask Register (F5 Index 40h).
31:6 X-Bus Expansion Base Address.
5:0 Address Range. This bit field must be set to 000001 for this register to operate correctly.
Index 14h-17h
Reserved. Reserved for possible future use by the Core Logic module.
Configuration of this register is programmed through the F5BAR1 Mask Register (F5 Index 44h)
Index 18h-1Bh
Reserved. Reserved for possible future use by the Core Logic module.
Configuration of this register is programmed through the F5BAR1 Mask Register (F5 Index 48h)
276
Core Logic Module - X-Bus Expansion Interface - Function 5
Located in the PCI Header Registers of F5 are six Base
Address Registers (F5BARx) used for pointing to the regis-
ter spaces designated for X-Bus Expansion support,
described later in this section.
Vendor Identification Register (RO)
Device Identification Register (RO)
PCI Command Register (R/W)
PCI Status Register (RO)
Device Revision ID Register (RO)
PCI Class Code Register (RO)
PCI Cache Line Size Register (RO)
PCI Latency Timer Register (RO)
PCI Header Type (RO)
PCI BIST Register (RO)
Base Address Register 0 - F5BAR0 (R/W)
Base Address Register 1 - F5BAR1 (R/W)
Base Address Register 2 - F5BAR2 (R/W)
Reset Value: 100Bh
Reset Value: 0505h
Reset Value: 0000h
Reset Value: 0280h
Reset Value: 00h
Reset Value: 068000h
Reset Value: 00h
Reset Value: 00h
Reset Value: 00h
Reset Value: 00h
Reset Value: 00000000h
Reset Value: 00000000h
Reset Value: 00000000h
AMD Geode™ SC3200 Processor Data Book