Figure 9-17. Input Timing Measurement Conditions; Figure 9-18. Pci Reset Timing - AMD Geode SC3200 Data Book

32581C
PCICLK
Input
POWER
V
IO
PCICLK
100 ms (typ)
POR#
PCIRST#
PCI
Signals
Note: The value of t
FAIL
500 mV.
376
t
V
TH
V
TEST
V
TL

Figure 9-17. Input Timing Measurement Conditions

TRI_STATE
is 500 ns (maximum) from the power rail which exceeds specified tolerance by more than

Figure 9-18. PCI Reset Timing

V
TEST
t
SU H
Input Valid V
) (
t
RST
) (
t
RST-CLK
AMD Geode™ SC3200 Processor Data Book
Electrical Specifications
V
TH
V
TL
V
TEST
t
FAIL
MAX
t
RST-OFF