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Electrical Specifications
Table 9-26. IDE Multiword DMA Data Transfer Timing Parameters
Symbol
Parameter
t
Cycle time (min)
0
t
IDE_IOR[0:1]#/IDE_IOW[0:1]# (min)
D
t
IDE_IOR[0:1]# data access (max)
E
t
IDE_IOR[0:1]# data hold (min)
F
t
IDE_IOW[0:1]#/IDE_IOW[0:1]# data setup
G
(min)
t
IDE_IOW[0:1]# data hold (min)
H
t
IDE_DACK[0:1]# to IDE_IOR[0:1]#/
I
IDE_IOW[0:1]# setup (min)
t
IDE_IOR[0:1]#/IDE_IOW[0:1]# to
J
IDE_DACK[0:1]# hold (min)
t
IDE_IOR[0:1]# negated pulse width (min)
KR
t
IDE_IOW[0:1]# negated pulse width (min)
KW
t
IDE_IOR[0:1]# to IDE_DREQ[0:1] delay
LR
(max)
t
IDE_IOW[0:1]# to IDE_DREQ0,1 delay
LW
(max)
t
IDE_CS[0:1]# valid to IDE_IOR[0:1]#/
M
IDE_IOW[0:1]# (min)
t
IDE_CS[0:1]# hold
N
t
IDE_DACK[0:1]# to TRI-STATE
Z
Note 1. t
is the minimum total cycle time, t
0
recovery time or command inactive time. The actual cycle time equals the sum of the command active time and the
command inactive time. The three timing requirements of t
requirement t
is greater than the sum of t
0
and/or t
to ensure that t
KR/KW
data.)
AMD Geode™ SC3200 Processor Data Book
0
480
215
150
5
100
20
0
20
50
215
120
40
50
15
20
is the minimum command active time, and t
D
and t
. (This means that a host implementation can lengthen t
D
KR/KW
is equal to or greater than the value reported in the device's IDENTIFY DEVICE
0
32581C
Mode
1
2
150
120
80
70
60
50
5
5
30
20
15
10
0
0
5
5
50
25
50
25
40
35
40
35
30
25
10
10
25
25
or t
KR
KW
, t
and t
, are met. The minimum total cycle time
0
D
KR/KW
Unit
Comments
ns
Note 1
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
is the minimum command
D
387
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