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Signal Definitions
3.3
Multiplexing Configuration
The tables that follow list multiplexing options and their
configurations. Certain multiplexing options may be chosen
per signal; others are available only for a group of signals.
Where ever a GPIO pin is multiplexed with another func-
tion, there is an optional pull-up resistor on this pin; after
Ball No.
Signal
AD3
IDE_ADDR0
AE1
IDE_ADDR1
U2
IDE_ADDR2
AC3
IDE_DATA0
AC1
IDE_DATA1
AC2
IDE_DATA2
AB4
IDE_DATA3
AB1
IDE_DATA4
AA4
IDE_DATA5
AA3
IDE_DATA6
AA2
IDE_DATA7
Y3
IDE_DATA8
Y2
IDE_DATA9
Y1
IDE_DATA10
W4
IDE_DATA11
W3
IDE_DATA12
V3
IDE_DATA13
V2
IDE_DATA14
V1
IDE_DATA15
Y4
IDE_IOR0#
AD1
IDE_IORDY0
AC4
IDE_DREQ0
AD2
IDE_IOW0#
AF2
IDE_CS0#
P2
IDE_CS1#
AD4
IDE_DACK0#
AA1
IDE_RST#
AF1
IRQ14
D11
TRDE#
AMD Geode™ SC3200 Processor Data Book
Table 3-5. Two-Signal/Group Multiplexing
Default
Configuration
IDE
PMR[24] = 0
Sub-ISA
PMR[12] = 0
system reset, the pull-up is present. This pull-up resistor
can be disabled by writing Core Logic registers. The config-
uration is without regard to the selected ball function. The
above applies to all pins multiplexed with GPIO, except
GPIO12, GPIO13, and GPIO16.
Alternate
Signal
TFT, PCI, GPIO, System
TFTD3
TFTD2
TFTD4
TFTD6
TFTD16
TFTD14
TFTD12
FP_VDD_ON
CLK27M
IRQ9
INTD#
GPIO40
DDC_SDA
DDC_SCL
GPIO41
TFTD13
TFTD15
TFTD17
TFTD7
TFTD10
TFTD11
TFTD8
TFTD9
TFTD5
TFTDE
TFTD0
TFTDCK
TFTD1
GPIO0
32581C
Configuration
PMR[24] = 1
GPIO
PMR[12] = 1
45
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