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Signal Definitions
3.4.18
JTAG Interface Signals (Continued)
Signal Name
Ball No.
TRST#
E29
3.4.19
Test and Measurement Interface Signals
Signal Name
Ball No.
GXCLK
V30
TEST3
V30
TEST2
AJ1
TEST1
AG4
TEST0
AH3
GTEST
F30
PLL6B
AG4
PLL5B
AJ1
PLL2B
AH3
SDTEST5
D28
SDTEST4
C31
SDTEST3
E28
SDTEST2
C28
SDTEST1
B29
SDTEST0
C30
TDP
D30
TDN
D31
AMD Geode™ SC3200 Processor Data Book
Type
Description
I
JTAG Test Reset. This signal has an internal weak pull-
up resistor.
For normal JTAG operation, this signal should be active
at power-up.
If the JTAG interface is not being used, this signal can be
tied low.
Type
Description
O
GX Clock. This signal is for internal testing only. For nor-
mal operation either program as FP_VDD_ON or leave
unconnected.
O
Internal Test Signal. This signal is used for internal test-
ing only. For normal operation leave unconnected, unless
programmed as FP_VDD_ON.
O
Internal Test Signals. These signals are used for internal
testing only. For normal operation, leave unconnected
O
unless programmed as one of their muxed options.
O
I
Global Test. This signal is used for internal testing only.
For normal operation this signal should be pulled down
with 1.5 KΩ.
I/O
PLL6, PLL5 and PLL2 Bypass. These signals are used
for internal testing only. For normal operation leave
I/O
unconnected.
I/O
O
Memory Internal Test Signals. These signals are used
for internal testing only. For normal operation, these sig-
nals should be programmed as one of their muxed
options.
O
O
O
O
O
I/O
Thermal Diode Positive / Negative. These signals are
for internal testing only. For normal operation leave
I/O
unconnected.
32581C
Mux
---
Mux
FP_VDD_ON+
TEST3
FP_VDD_ON+
GXCLK
PLL5B
PLL6B
PLL2B
---
TEST1
TEST2
TEST0
GPIO6+
DTR2#/BOUT2+
IDE_IOR1#
GPIO8+CTS2#+
IDE_DREQ1
SIN2
GPIO9+DCD2#+
IDE_IOW1#
GPIO10+DSR2#
+IDE_IORDY1
GPIO7+RTS2#+
IDE_DACK1#
---
---
67
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