Table 6-24. F5: Pci Header Registers For X-Bus Expansion Support Summary; Table 6-25. F5Bar0: I/O Control Support Registers Summary - AMD Geode SC3200 Data Book

Core Logic Module - Register Summary

Table 6-24. F5: PCI Header Registers for X-Bus Expansion Support Summary

Width
F5 Index (Bits) Type
00h-01h 16 RO
02h-03h 16 RO
04h-05h 16 R/W
06h-07h 16 RO
08h 8 RO
09h-0Bh 24 RO
0Ch 8 RO
0Dh 8 RO
0Eh 8 RO
0Fh 8 RO
10h-13h 32 R/W
14h-17h 32 R/W
18h-1Bh 32 R/W
1Ch-1Fh 32 R/W
20h-23h 32 R/W
24h-27h 32 R/W
28h-2Bh --- ---
2Ch-2Dh 16 RO
2Eh-2Fh 16 RO
30h-3Fh --- ---
40h-43h 32 R/W
44h-47h 32 R/W
48h-4Bh 32 R/W
4Ch-4Fh 32 R/W
50h-53h 32 R/W
54h-57h 32 R/W
58h 8 R/W
59h-FFh --- ---
60h-63h 32 R/W
64h-67h 32 R/W
68h-FFh --- ---

Table 6-25. F5BAR0: I/O Control Support Registers Summary

F5BAR0+ Width
I/O Offset (Bits) Type
00h-03h 32 R/W
04h-07h 32 R/W
08h-0Bh 32 R/W
AMD Geode™ SC3200 Processor Data Book
Name
Vendor Identification Register
Device Identification Register
PCI Command Register
PCI Status Register
Device Revision ID Register
PCI Class Code Register
PCI Cache Line Size Register
PCI Latency Timer Register
PCI Header Type Register
PCI BIST Register
Base Address Register 0 (F5BAR0) — Sets the base address for
the X-Bus Expansion support registers (summarized in
Table 6-25.)
Base Address Register 1 (F5BAR1) — Reserved for possible
future use by the Core Logic module.
Base Address Register 2 (F5BAR2) — Reserved for possible
future use by the Core Logic module.
Base Address Register 3 (F5BAR3) — Reserved for possible
future use by the Core Logic module.
Base Address Register 4 (F5BAR4) — Reserved for possible
future use by the Core Logic module.
Base Address Register 5 (F5BAR5) — Reserved for possible
future use by the Core Logic module.
Reserved
Subsystem Vendor ID
Subsystem ID
Reserved
F5BAR0 Base Address Register Mask
F5BAR1 Base Address Register Mask
F5BAR2 Base Address Register Mask
F5BAR3 Base Address Register Mask
F5BAR4 Base Address Register Mask
F5BAR5 Base Address Register Mask
F5BARx Initialized Register
Reserved
Scratchpad for Chip Number
Scratchpad for Configuration Block Address
Reserved
Name
I/O Control Register 1
I/O Control Register 2
I/O Control Register 3
32581C
Reset Reference
Value (Table 6-39)
100Bh Page 276
0505h Page 276
0000h Page 276
0280h Page 276
00h Page 276
068000h Page 276
00h Page 276
00h Page 276
00h Page 276
00h Page 276
00000000h Page 276
00000000h Page 276
00000000h Page 276
00000000h Page 277
00000000h Page 277
00000000h Page 277
00h Page 277
100Bh Page 277
0505h Page 277
00h Page 277
FFFFFFC1h Page 277
00000000h Page 278
00000000h Page 278
00000000h Page 278
00000000h Page 278
00000000h Page 278
00h Page 278
xxh Page 278
00000000h Page 278
00000000h Page 279
00h Page 279
Reset Reference
Value (Table 6-40)
010C0007h Page 280
00000002h Page 281
00009000h Page 281
183