Table of Contents
Advertisement
The AFG Output
Mode
Format
Aux Out/Aux In Level
Clock Source
248 HP E1340A Register-Based Programming
The AFG output mode consists of the following:
Setting the "Aux In" BNC port function.
Setting the "Aux Out" (marker) BNC port condition.
Setting the time base (reference) source.
Setting the "Aux In" and "Aux Out" sense levels.
Setting the waveform length
Setting the output mode
Selecting the Frequency Register
Selecting the RAM to output to the DAC.
The output mode is a two byte parameter. The format of the bytes is shown
in Table C-2.
Bit 7 of byte 1 sets the polarity of the signal at the "Aux Out" (marker) BNC
for the selected condition (bits 2 and 1). Bit 6 sets the polarity which
activates the selected event (bit 0). For bits 7 and 6, normal ("0") sets an
"active high" (positive transition) signal. Inverted ("1") sets an "active low"
(negative transition) signal.
The clock source bits (5 - 3) specify and control the AFG's reference clock
(oscillator). The sources:
External - external source is applied to the "Aux In" BNC. Bit 0
must be set to "1".
Gated - allows the reference to be gated by a gate signal applied to
the "Aux In" BNC. Bit 0 must be set to "1". A TTL "high" level
stops the output. A TTL "low" level enables the output.
Burst - allows a counted burst (see " Setting the Burst Count" ) of
cycles to occur when an internal or external trigger is received. This
source is set together with either the "internal burst" or "external
burst" mode (bits 4 - 2 of byte 2).
Internal - this source is the AFG's internal 42.94 MHz oscillator.
Input Data Register - allows waveform data to be downloaded to
the AFG's DAC through the Input Data Register (base + 0C
This source is set for the "direct DAC access" mode (bits 4 - 2 of
byte 2).
No clock - setting this condition stops the internal reference clock
or the acceptance of an external clock.
).
16
Appendix C
Advertisement
Table of Contents
