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The Status Register
Address
base + 04
Status Bit Precedence
236 HP E1340A Register-Based Programming
The flow and control of register-based programs are determined by the
Status Register. This register is continually monitored to determine when to
send a command, when to send a parameter, and when data is available.
15 - 8
FF 16
DONE
16
DONE. A zero (0) in bit 7 indicates that the operation performed by the
current command has finished. Bit 7 is set to one (1) when a command is
received and is being processed.
The validity of this bit is determined by bit 0. See " Status Bit Precedence"
for more information.
Burst Status. A zero (0) in bit 5 indicates the burst mode is set and a burst
is in progress. A one (1) indicates the burst mode is set and the burst is
complete. The bit is undefined if the burst mode is not set.
Pass/SysFail. A zero (0) in bit 3 indicates the AFG is executing a reset, or
is executing or has failed its self-test. A one (1) indicates the reset is
finished or the self-test passed.
Bit 2 performs the same function.
Response Buffer Full. A one (1) in bit 1 indicates data returned by a query
is in the Query Response Register. The bit is cleared (0) when the response
is read from the register.
Command Buffer Empty. A one (1) in bit 0 indicates a command or
parameter can be written to the Command or Parameter Register. The bit is
cleared (0) when the command or parameter is received. Bit 0 also
determines the validity of bit 7. See "Status Bit Precedence" for more
information.
In addition to the conditions the bits monitor, certain status bits indicate the
validity of other bits in the Status Register. This solves race situations
between selected bits.
When bit 0 is zero (0), bit 7 is invalid. This allows the AFG to set bit 7
(set it to one (1)) to indicate that a command or parameter is being
processed. When Bit 7 is zero (0), bit 1 is invalid. This allows the AFG
time to set those bits to the correct states based on the conditions they
represent.
7
6
5
1
Burst
Status
4
3
2
0
Pass/
Pass/Sys
Resp
SysFail
Fail
Buffer
1
0
Cmd
Buffer
Full
empty
Appendix C
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