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Aux Out
Aux In
RAM Bank
Appendix C
The AFG's "Aux Out" BNC port outputs the following TTL level signals.
The polarity of the signal is set by bit 7.
42 MHz osc. - this square wave signal is the AFG's internal
42.94 MHz reference clock. Bit 7 (polarity) is ignored.
Pulse/cycle - this signal is a marker pulse that is output at the
beginning of each waveform output segment (1 pulse per 4k RAM
bank). Bit 7 (polarity) is ignored.
Zero Cross - this signal is a marker pulse that is output each time
the output waveform crosses through 0V (positive or negative
transition). Bit 7 (polarity) is ignored.
Sweep sync - this signal is a marker pulse that is output at the
beginning of each sweep. Bit 7 (polarity) can be used.
The "Aux In" BNC connector accepts TTL level signals which activate the
following events based on the setting of bit 0. The bit is set based on the
clock source setting and mode setting.
Setting bit 0 to "0" enables an external signal to select the output
signal (wave hop), to select the output frequency (FSK), or to
trigger a counted burst. The external signal's rising edge selects the
waveform in RAM 0. Its falling edge selects the waveform in RAM
1. Similarly, its rising edge selects FSK frequency 1, and its falling
edge selects FSK Frequency 2. The sensing of the signal for wave
hopping , FSK, and external bursts can be inverted with bit 6.
Setting bit 0 to "1" enables an external reference clock to be applied
to the port. Bit 0 is also set to "1" when the output is to be gated on
and off.
The RAM Bank bits (bits 7 - 6 of byte 2) are used to select the waveform
stored in the RAM bank when the output function is set (see " Setting the
Output Function" ). The output mode (bits 4 - 2) or RAM size (bits 1 - 0)
may override the RAM bank bits.
HP E1340A Register-Based Programming 249
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