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AFG Reset
Sequence
Comments
Appendix C
The AFG is reset as indicated in Figure C-2.
Figure C-2. Register Access to Reset the AFG
1. The registers used are:
- Control Register (base + 04
- Status Register (base + 04
2. Writing a "1" to bit 1 prevents the AFG from asserting the SYSFAIL
line when it is reset. If SYSFAIL is enabled when a reset occurs, the
AFG is taken off-line by the system Resource Manager.
3. Writing a "1" to bits 1 and 0 resets the AFG while preventing the
AFG from asserting SYSFAIL . Writing a "0" to bit 0 turns the reset
function off.
4. Bit 2 of the Status Register is monitored to determine when the reset
is finished.
5. Writing a "0" to bit 1 re-enables SYSFAIL.
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HP E1340A Register-Based Programming 253
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