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Frequency Register
Output Mode
250 HP E1340A Register-Based Programming
The Frequency Register bit (bit 5) selects the output frequency stored in
Frequency Register 1 or Frequency Register 2 (command opcodes 1 and 2).
Frequency Register 1 contains:
fixed (continuous) frequency
sweep start frequency
first FSK frequency
Frequency Register 2 contains:
fixed (continuous) frequency
sweep stop frequency
second FSK frequency
The AFG output modes (bits 4 - 2) are:
Continuous (fixed) - output signal has a continuous (fixed)
frequency. This is the default mode.
FSK - output mode is frequency-shift keying. Bit 0 of byte 1 must
be set to "0" in order for a control signal (applied to the "Aux In"
BNC) to shift frequencies. The rising edge of the control signal
selects the frequency in Frequency Register 1. The falling edge of
the control signal selects Frequency Register 2. When this mode is
set, the Frequency Register bit (bit 5) is ignored.
Wave hop - output mode is wave hopping. Bit 0 of byte 1 must be
set to "0" in order for a control signal (applied to the "Aux In"
BNC) to select the output waveform. The rising edge of the control
signal selects the waveform in RAM 0. The falling edge of the
control signal selects the waveform in RAM 1. When this mode is
set, the RAM bank bits (7 - 6) and the RAM size bits (1 - 0) are
ignored.
Internal burst - this mode will output the number of cycles
specified by the burst count (opcode 8) and stop. This mode is set
together with the "burst" clock source (bits 5 - 3 of byte 1).
External burst - this mode will output the number of cycles
specified by the burst count (opcode 8) each time an external trigger
is received ("Aux In" BNC). This mode is set together with the
"burst" clock source (bits 5 - 3 of byte 1).
Sweep - this mode sets a linear sweep from the (start) frequency in
Frequency Register 1 to the (stop) frequency in Frequency Register
2. The RAM bank bits (7 -6) select the waveform which is swept.
Appendix C
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