Pattern Generator Self-Tests Description - Agilent Technologies 16800 Series Service Manual

5
Troubleshooting

Pattern Generator Self-Tests Description

92
Inter-module Flag Bits Test
The purpose of this test is to verify that the 4 Inter- module
Flag Bit Output lines can be driven out from the master chip
in the module and received by each chip in the module.
Global and Local Arm Lines Test
The purpose of this test is to verify that each Analysis chip
on the master board can receive the Local Arm signal, and
the Global Arm signal can be driven by the bottom and top
chips on the master board and received by all chips in the
module (master and slave). Note that the middle analysis
chip cannot drive the Global Arm signal (left unconnected).
Timing Zoom Memory BIST Test
This test verifies that the timing zoom SRAM embedded in
the analysis chips is functional.
Timing Zoom Memory Addr/Data Test
This test verifies connectivity of components within the
analysis chip. It verifies that the address, data, and clock
lines of the timing zoom circuitry is correct.
The self- tests for the pattern generator identify the correct
operation of major functional areas in the module.
Internal Loopback Test
The internal loopback test verifies the operation of the
module backplane interface IC. A walking ones pattern is
written into module memory at a specific memory location,
read, and compared with known values.
Passing the internal loopback test implies the module
backplane interface IC is functioning and the system is able
to write to module memory.
In case of error, the following diagnostic integer will be
displayed.
Bit#: 39 - 16
Memory Address
15 - 8
Expected Value
16800 Series Portable Logic Analyzers Service Guide
7 - 0
Actual Value