Memory Controller And Acquisition Memory; Master/Expander Connectors; Mainframe Interface And Control Fpga - Agilent Technologies 16800 Series Service Manual

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Theory of Operation

Memory Controller and Acquisition Memory

Master/Expander Connectors

Mainframe Interface and Control FPGA

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The Memory Controllers store data from the Acquisition ICs
into the Acquisition Memory array which is composed of
256 Mbit DDR DRAMs. They also unload data from the
memory array after an acquisition is complete, and they
deliver the data to the mainframe display system through
the mainframe interface connector. In addition they control
refresh of the RAM array and can perform a search of
stored data.
Connectors J9 through J13 and J15 route state and timing
clocks, calibration signals, data search signals, and control
from the Master card to all cards in the module.
Connectors J20 through J23 route pattern recognition signals
between all cards in a card set as well as control clocks
from the Master card to other cards in the set.
The Mainframe interface consists of an FPGA and the
Mainframe Interface Connector. The connector brings power
onto the card and provides for control of the card by the
analyzer mainframe. It also provides a path for unloading
acquired data to the analyzer display.
The FPGA converts bus signals generated by the mainframe
processor into control signals for the logic analyzer card. It
also provides centralized functions for the card such as I2C,
Calibration signals, Flag routing, and Timing mode sample
clock.
16800 Series Portable Logic Analyzers Service Guide