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Figure 86. SMBUS 2.0/SMLink Protocol
Host Controller and
Slave Interface
Intel
Note: Intel does not support external access of the ICH4-M's Integrated LAN Controller via the SMLink
interface. Also, Intel does not support access of the ICH4-M's SMBus Slave interface by the ICH4-M's
SMBus Host Controller. Refer to the Intel
Controller Datasheet for full functionality descriptions of the SMLink and SMBus interface.
10.6.1.
SMBus Architecture and Design Considerations
10.6.1.1.
SMBus Design Considerations
There is not a single SMBus design solution that will work for all platforms. One must consider the total
bus capacitance and device capabilities when designing SMBus segments. Routing SMBus to the PCI
slots makes the design process even more challenging since they add so much capacitance to the bus.
This extra capacitance has a large affect on the bus time constant which in turn affects the bus rise and
fall times.
Primary considerations in the design process are:
1. Device class (High/Low power). Most designs use primarily High Power Devices.
2. Are there devices that must run in S3?
3. Amount of V
®
Intel
852GM Chipset Platform Design Guide
SMBus
®
ICH4
SMLink
Wire OR
(optional)
_
current available, i.e. minimizing load of V
CC
SUSPEND
SPD Data
Temperature on
Thermal Sensor
SMBCLK
SMBDATA
SMLink0
SMLink1
Motherboard
LAN
Controller
®
82801DBM I/O Controller Hub 4 Mobile (ICH4-M)I/O
I/O Subsystem
Network
Interface Card
on PCI Bus
Microcontroller
SMbus-SMlink_IF
_
CC
SUSPEND.
171
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