Table of Contents
Advertisement
A
4
39
VR_VID[5:0]
3
19,37,39
PM_DPRSLPVR
6,19,37,39
PM_STPCPU#
39
ON_BOARD_VR_ON
3,39
PM_PSI#
32,37
VR_ON
1.2V_EV
2
1
A
B
IMVP IV
B
C
3..5,9,18..20,42,46
+VCCP
R1F13
1K
VR_VID_N
R1F14
C1F4
1K
0.1UF
39
VR_VID0
39
VR_VID1
ON_BOARD_VR_PWRGD
39
39
VR_VID2
VR_PWRGD_CK408#
6,39
CORE_VR_ON
39
39
VR_VID3
VOUT_EVMC_B39
46
39
VR_VID4
39
VR_VID5
C
D
5,6,8,9,11,15..18,20,21,23,26,31,33..36,38,39,45
8,15..18,20,23..25,27,33..35,38,39,45,46
3
R2G2
VR_VID_D0
5
+
2
1K
4
-
U2F1A
LM339
12
3
R2G1
VR_VID_D1
7
+
1K
6
-
12
3
R1G4
VR_VID_D2
9
+
14
1K
8
-
U2F1C
LM339
12
3
R1G3
VR_VID_D3
11
+
1K
10
-
12
3
R1G2
VR_VID_D4
5
+
2
1K
4
-
U1F1A
LM339
12
3
R1G1
VR_VID_D5
7
+
1K
6
-
12
Title
IMVP-IV & Mux Buffer
Size
Project:
A
Intel Celeron M / 852GM CRB C26116
Date:
Wednesday, January 12, 2005
D
E
+V3.3S
4
+V5S
R2F7
10K
SIO_VR_VID0 34
C1F3
R2F8
0.1UF
10K
1
SIO_VR_VID1 34
U2F1B
LM339
R1F9
3
10K
SIO_VR_VID2 34
R1F8
10K
13
SIO_VR_VID3 34
U2F1D
LM339
R1F11
10K
SIO_VR_VID4 34
2
R1F10
C2F5
10K
0.1UF
1
SIO_VR_VID5 34
U1F1B
LM339
1
Document Number
Rev
4.403
Sheet
40
of
51
E
Advertisement
Table of Contents
