Intel 852GM Design Manual page 7

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10.4.2.
10.4.3.
10.4.4.
10.4.5.
10.5. IOAPIC (I/O Advanced Programmable Interrupt Controller) .......................................169
10.5.1.
10.6. SMBus 2.0/SMLink Interface .......................................................................................170
10.6.1.
10.7. FWH .............................................................................................................................173
10.7.1.
10.7.2.
10.7.3.
10.7.4.
10.8. RTC..............................................................................................................................175
10.8.1.
10.8.2.
10.8.3.
10.8.4.
10.8.5.
10.8.6.
10.8.7.
10.8.8.
10.9. Internal LAN Layout Guidelines ...................................................................................181
10.9.1.
10.9.2.
®
Intel 852GM Chipset Platform Design Guide
10.4.1.5. USB 2.0 Trace Length Pair Matching ...........................................166
10.4.1.6. USB 2.0 Trace Length Guidelines ................................................166
Plane Splits, Voids, and Cut-Outs (Anti-Etch)..............................................166
10.4.2.1. VCC Plane Splits, Voids, and Cut-Outs (Anti-Etch)......................167
10.4.2.2. GND Plane Splits, Voids, and Cut-Outs (Anti-Etch) .....................167
USB Power Line Layout Topology ...............................................................167
EMI Considerations......................................................................................168
10.4.4.1. Common Mode Chokes ................................................................168
ESD ..............................................................................................................169
IOAPIC Disabling Options............................................................................170
10.5.1.1. Recommended Implementation ....................................................170
SMBus Architecture and Design Considerations.........................................171
10.6.1.1. SMBus Design Considerations .....................................................171
10.6.1.2. General Design Issues and Notes ................................................172
10.6.1.3. High Power and Low Power Mixed Architecture...........................172
10.6.1.4. Calculating the Physical Segment Pull-Up Resistor .....................172
FWH Decoupling ..........................................................................................173
In Circuit FWH Programming .......................................................................174
FWH INIT# Voltage Compatibility ................................................................174
FWH V Design Guidelines ........................................................................175
PP
RTC Crystal..................................................................................................176
External Capacitors......................................................................................177
RTC Layout Considerations .........................................................................178
RTC External Battery Connections ..............................................................178
RTC External RTCRST# Circuit...................................................................179
V DC Voltage and Noise Measurements................................................180
BIAS
SUSCLK .......................................................................................................180
RTC-Well Input Strap Requirements ...........................................................180
ICH4-M - LAN Connect Interface Guidelines ..............................................182
10.9.1.1. Bus Topologies .............................................................................182
10.9.1.1.1. LOM (LAN On Motherboard) Point-To-Point
Interconnect ................................................................182
10.9.1.2. Signal Routing and Layout............................................................183
10.9.1.3. Crosstalk Consideration................................................................183
10.9.1.4. Impedances...................................................................................183
10.9.1.5. Line Termination ...........................................................................184
10.9.1.6. Terminating Unused LAN Connect Interface Signals ...................184
Intel 82562ET / Intel 82562 EM Guidelines .................................................184
10.9.2.1. Guidelines for Intel 82562ET / Intel 82562EM Component
Placement .....................................................................................184
10.9.2.2. Crystals and Oscillators ................................................................184
10.9.2.3. Intel 82562ET / Intel 82562EM Termination Resistors .................185
10.9.2.4. Critical Dimensions .......................................................................185
10.9.2.4.1. Distance from Magnetics Module to RJ-45
(Distance A) ................................................................186
10.9.2.4.2. Distance from Intel 82562ET to Magnetics Module
(Distance B) ................................................................186
10.9.2.5. Reducing Circuit Inductance .........................................................186
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