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7.3.4.
7.3.5.
7.3.6.
7.3.7.
7.3.8.
7.4.
System Memory Compensation...................................................................................125
7.5.
SMVREF Generation ...................................................................................................125
7.6.
DDR Power Delivery....................................................................................................125
7.7.
External Thermal Sensor Based Throttling (ETS#) .....................................................126
7.7.1.
7.7.2.
7.7.3.
8.
Integrated Graphics Display Port .............................................................................................129
8.1.
Analog RGB/CRT Guidelines ......................................................................................129
8.1.1.
8.1.2.
8.1.3.
8.1.4.
8.1.5.
8.1.6.
8.1.7.
8.2.
LVDS Transmitter Interface .........................................................................................134
8.2.1.
®
Intel
852GM Chipset Platform Design Guide
7.3.3.3.
Clock Package Length Table ..........................................................89
7.3.3.4.
Clock Routing Example...................................................................89
7.3.3.4.1.
Device Support .............................................................90
Data Signals - SDQ[64:0], SDM[7:0], SDQS[7:0]..........................................90
7.3.4.1.
Data Bus Topology..........................................................................92
7.3.4.2.
SDQS to Clock Length Matching Requirements.............................94
7.3.4.3.
Data to Strobe Length Matching Requirements..............................95
7.3.4.4.
SDQ to SDQS Mapping ..................................................................96
7.3.4.5.
SDQ/SDQS Signal Package Lengths .............................................98
7.3.4.6.
DDR Data Routing Example .........................................................100
Control Signals - SCKE[3:0], SCS#[3:0] .....................................................100
7.3.5.1.
Control Signal Topology................................................................101
7.3.5.2.
Control Signal Routing Guidelines ................................................102
7.3.5.3.
Control to Clock Length Matching Requirements .........................103
7.3.5.4.
DDR Control Routing Example .....................................................105
7.3.5.5.
Control Group Package Length Table ..........................................106
7.3.6.1.
Command Topology 1...................................................................106
7.3.6.2.
Command Topology 1 Routing Guidelines ...................................108
7.3.6.3.
Command Topology 1 Length Matching Requirements ...............109
7.3.6.4.
Command Topology 2...................................................................111
7.3.6.5.
Command Topology 2 Routing Guidelines ...................................112
7.3.6.6.
Command Topology 2 Length Matching Requirements ...............113
7.3.6.7.
Command Topology 2 Routing Example ......................................115
7.3.6.8.
Command Topology 3...................................................................116
7.3.6.9.
Command Topology 3 Routing Guidelines ...................................117
7.3.6.10.
Command Topology 3 Length Matching Requirements ...............118
7.3.6.11.
Command Group Package Length Table .....................................120
CPC Signals - SMA[5,4,2,1], SMAB[5,4,2,1]...............................................121
7.3.7.1.
CPC Signal Topology....................................................................122
7.3.7.2.
CPC Signal Routing Guidelines ....................................................122
7.3.7.3.
CPC to Clock Length Matching Requirements .............................123
7.3.7.4.
CPC Group Package Length Table ..............................................125
Feedback - RCVENOUT#, RCVENIN#.......................................................125
ETS# Usage Model ......................................................................................126
ETS# Design Guidelines ..............................................................................126
Thermal Sensor Placement Guidelines .......................................................127
RAMDAC/Display Interface..........................................................................129
Reference Resistor (REFSET).....................................................................129
RAMDAC Board Design Guidelines.............................................................130
RAMDAC Routing Guidelines ......................................................................131
DAC Power Requirements ...........................................................................133
HSYNC and VSYNC Design Considerations...............................................134
DDC and I2C Design Considerations ..........................................................134
Length Matching Constraints .......................................................................135
5
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