Intel 852GM Design Manual page 11

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Figures
Figure 1. Intel 852GM Chipset System Block Diagram........................................................... 22
Figure 2. Recommended Board Stack-Up Dimensions .......................................................... 28
Figure 3. Cross-Sectional View of 2:1 Ratio............................................................................ 32
Figure 4. Processor Topology ................................................................................................. 34
Figure 5. SS Topology for Address and Data.......................................................................... 36
Figure 6. FSB Host Data Routing Example Layer 3................................................................ 36
Figure 7. FSB Host Address Routing Example Layer 3 .......................................................... 37
Figure 8. FSB Host Data Routing Example Layer 6................................................................ 37
Figure 9. FSB Host Address Routing Example Layer 6 .......................................................... 38
Figure 10. Routing Illustration for Topology 1A ....................................................................... 40
Figure 11. Routing Illustration for Topology 1B ....................................................................... 41
Figure 12. Routing Illustration for Topology 1C....................................................................... 42
Figure 13. Routing Illustration for Topology 2A ....................................................................... 43
Figure 14. Routing Illustration for Topology 2B ....................................................................... 43
Figure 15. Routing Illustration for Topology 2C....................................................................... 44
Figure 16. Routing Illustration for Topology 3 ......................................................................... 45
Figure 17. Voltage Translation Circuit for 3.3-V Receivers ..................................................... 45
Figure 18. GTLREF Routing.................................................................................................... 50
Figure 19. Mobile Intel Pentium 4 Processor-M COMP[1:0] Resistive Compensation ........... 51
Figure 20. Common Clock Topology....................................................................................... 55
Figure 21. Layer 6 FSB Source Synchronous Signals GND Referencing to Layer 5 ............. 57
Figure 22. Layer 3 FSB Source Synchronous Signals............................................................ 58
Figure 23. Routing Illustration for Topology 1A ....................................................................... 65
Figure 24. Routing Illustration for Topology 1B ....................................................................... 66
Figure 25. Routing Illustration for Topology 1C....................................................................... 67
Figure 26. Routing Illustration for Topology 2A ....................................................................... 67
Figure 27. Routing Illustration for Topology 2B ....................................................................... 68
Figure 28. Routing Illustration for Topology 2C....................................................................... 69
Figure 29. Routing Illustration for Topology 3 ......................................................................... 70
Figure 30. Voltage Translation Circuit ..................................................................................... 71
Figure 31. Processor RESET# Signal Routing Topology with NO ITP700FLEX Connector .. 71
Figure 32. Processor RESET# Signal Routing Topology with ITP700FLEX Connector......... 72
Figure 33. Processor RESET# Signal Routing Example with ITP700FLEX Debug Port........ 73
Figure 34. Processor and GMCH Host Clock Layout Routing Example ................................. 74
Figure 35. Processor GTLREF Voltage Divider Network ........................................................ 75
Figure 36. Processor GTLREF Motherboard Layout .............................................................. 76
Figure 37. Processor COMP[2] & COMP[0] Resistive Compensation.................................... 77
Figure 38. Processor COMP[3] & COMP[1] Resistive Compensation.................................... 77
Figure 39. Processor COMP[3:0] Resistor Layout .................................................................. 78
Figure 40. Processor COMP[1:0] Resistor Alternative Primary Side Layout .......................... 78
Figure 41. COMP2 & COMP0 27.4-Ω Traces ......................................................................... 79
Figure 42. V
Figure 43. DDR Clock Routing Topology SCK/SCK#[5:0] ...................................................... 85
Figure 44. DDR Clock Trace Length Matching Diagram......................................................... 88
Figure 45. Clock Signal Routing Example............................................................................... 90
Figure 46. Data Signal Routing Topology ............................................................................... 92
Figure 47. SDQS to Clock Trace Length Matching Diagram .................................................. 95
Figure 48. SDQ/SDM to SDQS Trace Length Matching Diagram .......................................... 97
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Intel 852GM Chipset Platform Design Guide
/V Routing Example....................................................................... 80
CCSENSE SSSENSE
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