Intel 852GM Design Manual page 273

Chipset platform
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A
Intel 852GM CUSTOMER REFERENCE PLATFORM
SCHEMATIC ANNOTATIONS AND BOARD INFORMATION
Voltage Rails
4
+VDC
Primary DC system power supply (10 to 21V)
+VCC_IMVP
Core/VTT voltage for processor & VTT for Montara-GML
+VCC_VID
1.2V for processor PLL and VID circuitry
+V1.2S
1.2V for Montara-GML core/hub interface
+V1.25S
1.25V DDR Termination voltage
+V1.5S
1.5V switched power rail (off in S3-S5)
+V1.5ALWAYS
1.5V always on power rail
+V1.5
1.5V power rail (off in S4-S5)
+V2.5
2.5V power rail for DDR
+V3.3ALWAYS
3.3V always on power rail
+V3.3
3.3V power rail (off in S4-S5)
+V3.3S
3.3V switched power rail (off in S3-S5)
+V5ALWAYS
5.0V for ICH4M's VCC5REFSUS
+V5
5.0V power rail (off in S4-S5)
+V5S
5.0V switched power rail (off in S3-S5)
3
+V12S
12.0V switched power rail (off in S3-S5)
-V12S
-12.0V switched power rail for PCI (off in S3-S5)
PCI Devices
Device
IDSEL #
Slot 1
AD16
Slot 2
AD17
Slot 3
AD18
Docking
AD28
LAN
(AD24 internal)
2
Power States
SIGNAL
STATE
SLP_S1#
Full ON
HIGH
S1M (Power On Suspend)
LOW
1
S3 (Suspend to RAM)
LOW
S4 (Suspend To Disk)
LOW
S5 / Soft OFF
LOW
A
B
REQ/GNT #
Interrupts
PC/PCI
1
1
F, G, H, E
A
2
2
G, F, E, H
A
3
3
C, D, B, A
A
(E, F, G, H optional)
4
4
D, A, B, C
B
(E internal)
SLP_S3#
SLP_S4#
SLP_S5#
+V*ALWAYS
+V*
HIGH
HIGH
HIGH
ON
ON
HIGH
HIGH
HIGH
ON
ON
LOW
HIGH
HIGH
ON
ON
LOW
LOW
HIGH
ON
OFF
LOW
LOW
LOW
ON
OFF
B
C
2
I C / SMB Addresses
Device
Address
Hex
Bus
Clock Generator
1101 001x
D2
SMB_ICH_S
Spread Spectrum Clock
1101 010x
D4
SMB_ICH_S
SO-DIMM0
1010 000x
A0
SMB_ICH_S
SO-DIMM1
1010 001x
A2
SMB_ICH_S
Thermal Sensor Header
1001 000x
90
SMB_ICH
LVDS Backlight Inverter
____ ____
__
SMB_ICH
Dock Connector
____ ____
__
SMB_ICH
Smart Battery
0001 011x
16
SMB_SB
Smart Battery Charger
0001 001x
12
SMB_SB
Smart Selector
0001 010x
14
SMB_SB
Bluetooth Header
____ ____
__
SMB_SB
LPC Pwr Mngmnt Header
____ ____
__
SMB_SB
LPC Pwr Mngmnt Header
____ ____
__
SMB_THRM
Thermal Diode
1001 110x
9C
SMB_THRM
EV Support:
DV0-DV3
0101 0001
51
SMB_ICH
V5-V8
0101 0010
52
SMB_ICH
PV0-PV3
0101 0011
53
SMB_ICH
DV4
0101 0100
54
SMB_ICH
V9-V12
0101 0101
55
SMB_ICH
I1-I4
0101 0110
56
SMB_ICH
EP1-EP4
0101 0111
57
SMB_ICH
PV4
0101 0100
58
SMB_ICH
V1-V4
0101 1001
59
SMB_ICH
LEDs and Switches
LED
Page
Primary IDE
27
Secondary IDE
27
SMC/KBC Num Lock
32
SMC/KBC Scroll Lock
32
SMC/KBC Caps Lock
32
S0 State
38
S1 State
38
S3 State
38
S4 State
38
S5 State
38
VID0
39
VID1
39
VID2
39
VID3
39
VID4
39
Switch
Page
Virtual Battery On/Off
32
Lid
32
Power On/Off
44
Reset
44
+V*S
Clocks
ON
ON
ON
LOW
OFF
OFF
OFF
OFF
OFF
OFF
C
D
Default Jumper Settings
Jumper
Default
Option
Description
J7B1
1-2
1-X
GMCH Strap: PSB Voltage
J7B3
1-X
1-2
GMCH Strap: DVO Strap
J7B4
1-X
1-2
GMCH Strap: Clock Config
J7B5
1-X
1-2
GMCH Strap: Clock Config
J7B6
1-X
1-2
GMCH Strap: Clock Config
J6E1
2-3
1-2
LVDS EV
J2J3
1-X
1-2
CMOS Clear
J8J2
2-3
1-2
CRB/SV Detect
J9E2
1-2
2-3
Moon ISA Support
J9E4
1-2
2-3
Moon ISA Support
J9E5
2-3
1-2
Moon ISA Support
J9B1
1-X
1-2
SMC/KBC Programming
J9A1
1-X
1-2
KBC 60/64 Decode Disable
J8A2
1-2
2-3
SMC/KBC Disable
J8A1
1-2
1-X
INIT Clock Disable
J9H1
1-X
1-2
Port 80-81/82-83 Select
J9G2
1-2
2-3
SIO Disable
J1F1
1-X
1-2
Manual VID Strap Enable
J1G1
1-2
2-3
VID0 Strap
J1G2
1-2
2-3
VID1 Strap
J1G3
1-2
2-3
VID2 Strap
J1G4
1-2
2-3
VID3 Strap
J1H1
1-2
2-3
VID4 Strap
J3G1
1-X
1-2 or 2-3
DDR EV Support
J3G2
Wake Events
Reference
RI# (Ring Indicate) from serial port
DS2J2
PME# (Power Management Event) from PCI/mini-PCI slots,
DS2J1
ADD slot, LPC slot
DS8A1
Jordan I/O from Kinnereth+
DS8A2
LID switch attached to SMC
DS8B1
DS1H1
USB
DS1H3
AC97 wake on ring
DS1H2
SmLink for AOL II
DS2H2
Hot Key from the scan matrix keyboard
DS2H1
DS1J3
DS1J2
Net Naming Conventions
DS1J1
DS2J4
DS2J3
Suffix
#
=
Active Low signal
Reference
SW8A1
Prefix
SW9A1
H
=
Host
SW8J1
M
=
DDR Memory
SW7J1
PCB Footprints
SOT-23
1
3
2
Title
Notes and Annotations
Size
Project:
A
Intel 852GM CRB
D
E
4
Page
08
08
08
08
08
08
19
19
23
23
23
32
32
32
33
33
34
39
39
39
39
3
39
39
43
2
TP = Test Point (does not
connect anywhere
else)
As seen from top
SOT23-5
1
5
2
1
3
4
Document Number
Rev
A#
2
of
59
E

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