Intel 852GM Design Manual page 4

4.5. Mobile Intel Pentium 4 Processor-M and Intel 852GM Chipset FSB Signal Package
Lengths ......................................................................................................................... 46
4.5.1.
4.5.2.
5. Intel Celeron M Processor Front Side Bus Design Guidelines .................................................. 52
5.1. Intel Celeron M Processor Front Side Bus Design Recommendations ........................ 52
5.2. Recommended Stack-up Routing and Spacing Assumptions ...................................... 52
5.2.1.
5.2.2.
5.3. Common Clock Signals ................................................................................................. 53
5.3.1.
5.4. Source Synchronous Signals General Routing Guidelines .......................................... 56
5.4.1.
5.4.2.
5.4.3.
5.4.4.
5.4.5.
5.5. Asynchronous Signals................................................................................................... 64
5.5.1.
5.5.2.
5.5.3.
5.5.4.
5.5.5.
5.5.6.
5.5.7.
5.5.8.
5.6. Processor RESET# Signal ............................................................................................ 71
5.6.1.
5.7. Processor and GMCH Host Clock Signals.................................................................... 73
5.8. Processor GTLREF Layout and Routing Recommendations ....................................... 74
5.9. AGTL+ I/O Buffer Compensation .................................................................................. 76
5.9.1.
5.10. Intel Celeron M Processor Front Side Bus Strapping and Debug Port......................... 79
5.11. Processor V
6. Processor Power Delivery Requirements .................................................................................. 81
7. System Memory Design Guidelines (DDR-SDRAM) ................................................................. 83
7.1. Length Matching and Length Formulas......................................................................... 84
7.2. Package Length Compensation .................................................................................... 84
7.3. Topologies and Routing Guidelines .............................................................................. 85
7.3.1.
7.3.2.
7.3.3.
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Mobile Intel Pentium 4 Processor-M GTLREF Layout and Routing
Recommendations......................................................................................... 50
AGTL+ I/O Buffer Compensation .................................................................. 50
4.5.2.1. Mobile Intel Pentium 4 Processor-M AGTL+ I/O Buffer
Compensation ................................................................................ 51
Trace Space to Trace - Reference Plane Separation Ratio ......................... 52
Trace Space to Trace Width Ratio ................................................................ 53
Processor Common Clock Signal Package Length Compensation .............. 54
Source Synchronous Signal Length Matching Constraints ........................... 58
Package Length Compensation .................................................................... 58
Source Synchronous - Data Group .............................................................. 59
Source Synchronous - Address Group......................................................... 60
Intel Celeron M Processor and Intel 852GM Chipset GMCH FSB Signal
Package Lengths ........................................................................................... 61
Topology 1A: Open Drain (OD) Signals Driven by the Processor - IERR#.. 65
Topology 1B: Open Drain (OD) Signals Driven by the Processor - FERR#
and THERMTRIP#......................................................................................... 65
Topology 1C: Open Drain (OD) Signals Driven by the Processor -
PROCHOT#................................................................................................... 66
Topology 2A: Open Drain (OD) Signals Driven by ICH4-M - PWRGOOD... 67
Topology 2B: CMOS Signals Driven by ICH4-M - DPSLP# ......................... 68
Topology 2C: CMOS Signals Driven by ICH4-M - LINT0/INTR, LINT1/NMI,
A20M#, IGNNE#, SLP#, SMI#, and STPCLK# ............................................. 68
Topology 3: CMOS Signals Driven by ICH4-M to CPU and FWH - INIT# ... 69
Voltage Translation Logic .............................................................................. 70
Processor RESET# Routing Example ........................................................... 72
Processor AGTL+ I/O Buffer Compensation ................................................. 76
/V Design Recommendations ............................................. 80
CCSENSE SSSENSE
Clock Signals - SCK[4,3,1,0], SCK#[4,3,1,0]................................................ 85
Clock Topology Diagram ............................................................................... 85
DDR Clock Routing Guidelines ..................................................................... 86
7.3.3.1. Clock Length Matching Requirements ........................................... 87
7.3.3.2. Clock Reference Lengths ............................................................... 87
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Intel 852GM Chipset Platform Design Guide
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