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A
U2E1A
8
H_A#[31:3]
H_A#3
P4
A3#
H_A#4
U4
A4#
H_A#5
V3
A5#
H_A#6
R3
A6#
H_A#7
V2
A7#
H_A#8
W1
A8#
H_A#9
T4
A9#
H_A#10
W2
A10#
H_A#11
4
Y4
A11#
H_A#12
Y1
A12#
H_A#13
U1
A13#
H_A#14
AA3
A14#
H_A#15
Y3
A15#
H_A#16
AA2
A16#
U3
8
H_ADSTB#0
ADSTB#0
8
H_REQ#[4:0]
H_REQ#0
R2
REQ0#
H_REQ#1
P3
REQ1#
H_REQ#2
T2
REQ2#
H_REQ#3
P1
REQ3#
H_REQ#4
T1
REQ4#
8
H_A#[31:3]
H_A#17
AF4
A17#
H_A#18
AC4
A18#
H_A#19
AC7
A19#
H_A#20
AC3
A20#
H_A#21
AD3
A21#
H_A#22
AE4
A22#
H_A#23
AD2
A23#
H_A#24
AB4
A24#
H_A#25
AC6
A25#
H_A#26
AD5
A26#
H_A#27
AE2
3
A27#
H_A#28
AD6
A28#
H_A#29
AF3
A29#
H_A#30
AE1
A30#
H_A#31
AF1
A31#
AE5
8
H_ADSTB#1
ADSTB#1
C2
18
H_A20M#
A20M#
D3
18
H_FERR#
FERR#
A3
18
H_IGNNE#
IGNNE#
C6
18,37
H_STPCLK#
STPCLK#
D1
18,37
H_INTR
LINT0
D4
18,37
H_NMI
LINT1
B4
18,37
H_SMI#
SMI#
Processor-Skt
2
5,6,8,9,11,15..18,20,21,23,26,31,33..36,38..40,43,45,51
Layout note:
COMP0 and COMP2 need to be Zo=27.4ohm traces. Best
estimate is 18mil wide trace for outer layers and 14mil
if on internal layer. See DG of
Processor.Traces
should be shorter than 0.5". Refer to latest CS layout
COMP1, COMP3 should be routed as Zo=55ohm
traces shorter than 0.5"
Comp0
Comp1
Comp2
Comp3
1
R2R1
R2R2
R3R2
54.9_1%
27.4_1%
54.9_1%
A
B
N2
H_ADS#
8
ADS#
L1
H_BNR#
8
BNR#
J3
H_BPRI#
8
BPRI#
L4
H_DEFER# 8
DEFER#
H2
H_DRDY# 8
DRDY#
M2
H_DBSY# 8
DBSY#
N4
BR0#
H_BR0#
8
H_IERR#
A4
IERR#
B5
H_INIT#
INIT#
J2
H_LOCK# 8
LOCK#
H_CPURST# 5,8
B11
RESET#
H1
H_RS#0
8
RS0#
K1
H_RS#1
8
RS1#
L2
H_RS#2
8
RS2#
M3
H_TRDY# 8
TRDY#
K3
HIT#
H_HIT#
8
K4
HITM#
H_HITM#
8
C8
H_BPM0_ITP# 5
BPM#0
B8
H_BPM1_ITP# 5
BPM#1
A9
H_BPM2_ITP# 5
BPM#2
C9
H_BPM3_ITP# 5
BPM#3
A10
H_BPM4_PRDY# 5
PRDY#
B10
H_BPM5_PREQ# 5
PREQ#
A13
H_TCK 5
TCK
C12
TDI
A12
H_TDO 5
TDO
C11
H_TMS 5
TMS
B13
TRST#
H_TRST# 5
A7
DBR#
ITP_DBRESET# 5,45,46
H_PROCHOT#
R3E1
B17
PROCHOT#
B18
H_THERMDA 5
THERMDA
A18
H_THERMDC 5
THERMDC
C17
PM_THRMTRIP# 19
THERMTRIP#
A15
ITP_CLK1
CLK_ITP_CPU# 6
A16
ITP_CLK0
CLK_ITP_CPU 6
B14
CLK_CPU_BCLK# 6
BCLK1
B15
CLK_CPU_BCLK 6
BCLK0
+V3.3S
R4F4
330
6
6,8
CK408_SEL1
CR4F1B
2
3904
1
CR4F1A
3904
R3R3
27.4_1%
B
C
+VCCP
4,5,9,18..20,40,42,43,46
R2E1
56
Place testpoint on
18,37
H_IERR# with a GND
0.1" away
8
H_D#[63:0]
+VCCP 4,5,9,18..20,40,42,43,46
H_TDI pullup (R3T3) must
be placed within 300ps of
CPU TDI pin (within 2")
R3T3
150
TDI_FLEX 5
+VCCP 4,5,9,18..20,40,42,43,46
56
8
H_DSTBN#0
8
H_DSTBP#0
8
H_DINV#0
4,5,9,18..20,40,42,43,46
+VCCP
8
H_DSTBN#1
R4D2
8
H_DSTBP#1
1K_1%
8
H_DINV#1
R4F5
H_GTLREF
1.3K
0.5" max length
46
5%
R3D1
2K_1%
3
J3F3
CPU_BSEL0_D
CPU_BSEL0
5
1
R4F2 330
4
J3F3 should open to
R4F3
support Celeron M
1K
C
D
U2E1B
H_D#0
A19
D0#
D32#
H_D#1
A25
D1#
D33#
H_D#2
A22
D2#
D34#
H_D#3
B21
D3#
D35#
H_D#4
A24
D4#
D36#
H_D#5
B26
D5#
D37#
H_D#6
A21
D6#
D38#
H_D#7
B20
D7#
D39#
H_D#8
C20
D8#
D40#
H_D#9
B24
D9#
D41#
H_D#10
D24
D10#
D42#
H_D#11
E24
D11#
D43#
H_D#12
C26
D12#
D44#
H_D#13
B23
D13#
D45#
H_D#14
E23
D14#
D46#
H_D#15
C25
D15#
D47#
C23
DSTBN0#
DSTBN2#
C22
DSTBP0#
DSTBP2#
D25
DINV0#
DINV2#
H_D#16
H23
D16#
D48#
H_D#17
G25
D17#
D49#
H_D#18
L23
D18#
D50#
H_D#19
M26
D19#
D51#
H_D#20
H24
D20#
D52#
H_D#21
F25
D21#
D53#
H_D#22
G24
D22#
D54#
H_D#23
J23
D23#
D55#
H_D#24
M23
D24#
D56#
H_D#25
J25
D25#
D57#
H_D#26
L26
D26#
D58#
H_D#27
N24
D27#
D59#
H_D#28
M25
D28#
D60#
H_D#29
H26
D29#
D61#
H_D#30
N25
D30#
D62#
H_D#31
K25
D31#
D63#
K24
DSTBN1#
DSTBN3#
L24
DSTBP1#
DSTBP3#
J26
DINV1#
DINV3#
TP_GTLREF3
AC1
GTLREF3
COMP0
TP_GTLREF2
G1
GTLREF2
COMP1
TP_GTLREF1
E26
GTLREF1
COMP2
AD26
GTLREF0
COMP3
MISC
A1
NC0
B2
NC1
DPSLP#
DPWR#
TP_B_SEL1
C14
RSVD1
PWRGOOD
TP_NC_2
C3
RSVD2
SLP#
TP_NC_3
AF7
RSVD3
CPU_BSEL0_J
2
C16
RSVD4
TEST1
E1
PSI#
TEST2
PM_PSI#
39,40
Processor-Skt
R3T1 & R2T3 are to be stuffed
for A0 silicon and no_stuffed
for A1 and follow-on silicon
Title
Intel Celeron M Processor 1 of 2
Size
Project:
Intel Celeron M / 852GM CRB
Custom
Date:
Wednesday, January 12, 2005
D
E
4
H_D#[63:0] 8
H_D#32
Y26
H_D#33
AA24
H_D#34
T25
H_D#35
U23
H_D#36
V23
H_D#37
R24
H_D#38
R26
H_D#39
R23
H_D#40
AA23
H_D#41
U26
H_D#42
V24
H_D#43
U25
3
H_D#44
V26
H_D#45
Y23
H_D#46
AA26
H_D#47
Y25
W25
H_DSTBN#2 8
W24
H_DSTBP#2 8
T24
H_DINV#2 8
H_D#48
AB25
H_D#49
AC23
H_D#50
AB24
H_D#51
AC20
H_D#52
AC22
H_D#53
AC25
H_D#54
AD23
H_D#55
AE22
H_D#56
AF23
H_D#57
AD24
H_D#58
AF20
H_D#59
AE21
H_D#60
AD21
H_D#61
AF25
H_D#62
AF22
H_D#63
2
AF26
AE24
H_DSTBN#3 8
AE25
H_DSTBP#3 8
AD20
H_DINV#3 8
Comp0
+VCCP
P25
Comp1
4,5,9,18..20,40,42,43,46
P26
Comp2
AB2
Comp3
R2T1
AB1
330
B7
H_DPSLP# 7,18,37
C19
H_DPWR# 7
E4
H_PWRGD 18,37
A6
H_CPUSLP# 18,37
TEST1
C5
TEST2
F23
R3T1
R2T3
NO_STUFF_1K
NO_STUFF_1K
1
Document Number
Rev
C26116
4.403
Sheet
3
of
51
E
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