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A
8,15..18,20,23..25,34,35,38..41,43,45,46
34,37
IDE_SPWR_EN#
4
+V5S_IDE_S
8,15..18,20,23..25,34,35,38..41,43,45,46
R2H8
100K
U3H1D
SHMIDT4
9
8
R2W1
C2W1
74HC14
1M
0.1UF
Q3H1
BSS138
IDE_SPWR_EN#
1
3
<NO_STUFF>
8,15..18,20,23..25,34,35,38..41,43,45,46
2
26,45
IDE_PDACTIVE#
1
26
IDE_SDACTIVE#
A
B
+V5S
U3H1A
1
2
74HC14
+V5S
U3H1B
SHMIDT2
IDE_SRST#
3
4
74HC14
15,17,23,37,45
IDE_SPWR_EN_Q#
R2G15
R2G14
IDE_SPWR_EN
1M
1
Q3G1
100K
2N7002
IDE Activity LEDs
+V5S
R2J6
470
IDE_PLED
DS2J2
GREEN
+V5S_IDE_S
R2J3
470
IDE_SDACTIVE#_Q
1
2
DS2J1
GREEN
B
C
Secondary IDE Power
C2H1
0.1UF
U3H1E
74HC14
IDE_SPWR_EN
IDE_SPWR2_D
11
10
R3H2
IDE_D_SRST# 26
47
8,15..18,20,23..25,34,35,38..41,43,45,46
+V12S
+V12S_IDE_S
C2G14
1000PF
Q2G4
IDE_SPWR_EN_D#
SI2307DS
1
19
AUDIO_PWRDN
19
AC_SYNC
R9F3
19
AC_SDATAIN1
R9F7
19
AC_SDATAIN0
R9G2
19
AC_BITCLK
C
D
8,15..18,20,23..25,34,35,38..41,43,45,46
R2H5
C2H2
1M
1
1000PF
R2H6 390K
U2H1A
IDE_SPWR2
SI4925DY
2
Note: Primary IDE
Power on Turner
DC/DC Module
7
8
R2H7
0.01_1%
+V5S
SPARE GATE
U3H1C
SHMIDT3
TP_SHMIDT_C
5
6
R3H1
74HC14
0
MDC Interposer Header
5,15,19..23,28,29,32,36..39,45,51
15,18..20,23,30,32,35,37,38,44,45
+V3.3
20..23,36,37,44,45
+V5
J9F4
1
2
3
4
5
6
7
8
9
10
SDATAIN1_D
33
11
12
33
SDATAIN0_D
13
14
15
16
17
18
AC_BITCLK_D
33
19
20
2x10-SHD-HDR
R9F2
10K
Layout Note:
Place R9F3, R9F7 and R9G2
0.1 to 0.4 inches from MDC
header based on topology
Title
IDE 2 of 2 / MDC INTERPOSER
Size
Project:
Intel Celeron M / 852GM CRB
A
Date:
Wednesday, January 12, 2005
D
E
+V5S
3
U2H1B
R2H1
SI4925DY
NO_STUFF_0
4
V5S_IDE_PD
+V12S_IDE_S
5
6
+V5S_IDE_S
J2H1
1
2
C2W3
C2J1
C2W2
+
C2H3
3
4
0.1UF
22UF
0.1UF
100uF
4Pin_PwrConn
For
Secondary
IDE Drive
Only
+V3.3ALWAYS
AC_SPKR 19
R9F5 33
AC_SDATAOUT_D
AC_SDATAOUT 19
R9F6 33
SDATAIN2_D
AC_SDATAIN2 19
AC_RST# 19
Document Number
Rev
C26116
4.403
Sheet
27
of
51
E
4
3
2
1
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