Intel 852GM Design Manual page 12

Figure 49. Data Signals Group Routing Example.................................................................. 100
Figure 50. Control Signal Routing Topology.......................................................................... 101
Figure 51. Control Signal to Clock Trace Length Matching Diagram .................................... 104
Figure 52. Control Signals Group Routing Example.............................................................. 105
Figure 53. Command Routing for Topology 1........................................................................ 107
Figure 54. Topology 1 Command Signal to Clock Trace Length Matching Diagram ............ 110
Figure 55. Command Routing Topology 2 ............................................................................. 111
Figure 56. Topology 2 Command Signal to Clock Trace Length Matching Diagram ............ 114
Figure 57. Example of Command Signal Group .................................................................... 115
Figure 58. Command Routing Topology 3 ............................................................................. 116
Figure 59. Topology 3 Command Signal to Clock Trace Length Matching Diagram ............ 119
Figure 60. Command per Clock Signal Routing Topology .................................................... 122
Figure 61. CPC Signals to Clock Length Matching Diagram................................................. 124
Figure 62. DDR Memory Thermal Sensor Placement ........................................................... 127
Figure 63. GMCH RAMDAC Routing Guidelines with Docking Connector ........................... 131
Figure 64. RAMDAC Routing w/ Resistor and Analog Switch Layout Example for Docking
Figure 65. Rset Resistor Placement ...................................................................................... 133
Figure 66. GVREF Reference Voltage................................................................................... 143
Figure 67. Hub Interface Routing Example............................................................................ 145
Figure 68. Single VREF/VSWING Voltage Generation Circuit for Hub Interface .................. 149
Figure 69. ICH4-M Locally Generated Reference Voltage Divider Circuit ............................ 150
Figure 70. GMCH Locally Generated Reference Voltage Divider Circuit.............................. 150
Figure 71. Individual HIVREF and HI_VSWING Voltage Reference Divider Circuits for
Figure 72. Individual HLVREF and PSWING Voltage Reference Divider Circuits for
Figure 73. Connection Requirements for Primary IDE Connector......................................... 154
Figure 74. Connection Requirements for Secondary IDE Connector.................................... 155
Figure 75. PCI Bus Layout Example...................................................................................... 158
Figure 76. ICH4-M AC'97 - Codec Connection..................................................................... 159
Figure 77. ICH4-M AC'97 - AC_BIT_CLK Topology ............................................................. 160
Figure 78. ICH4-M AC'97 - AC_SDOUT/AC_SYNC Topology............................................. 160
Figure 79. ICH4-M AC'97 - AC_SDIN Topology ................................................................... 161
Figure 80. Example Speaker Circuit ...................................................................................... 164
Figure 81. Recommended USB Trace Spacing..................................................................... 165
Figure 82. USBRBIAS Connection ........................................................................................ 166
Figure 83. Good Downstream Power Connection ................................................................. 168
Figure 84. Common Mode Choke Schematic........................................................................ 168
Figure 85. Minimum IOAPIC Disable Topology ..................................................................... 170
Figure 86. SMBUS 2.0/SMLink Protocol................................................................................ 171
Figure 87. High Power/Low Power Mixed V
Figure 88. Voltage Translation Circuit for 3.3-V Receivers ................................................... 174
Figure 89. FWH VPP Isolation Circuitry................................................................................. 175
Figure 90. RTCX1 and SUSCLK Relationship in ICH4-M ..................................................... 175
Figure 91. External Circuitry for the ICH4-M Where the Internal RTC Is Not Used .............. 176
Figure 92. External Circuitry for the ICH4-M RTC ................................................................. 176
Figure 93. Diode Circuit to Connect RTC External Battery ................................................... 179
Figure 94. RTCRST# External Circuit for the ICH4-M RTC .................................................. 179
Figure 95. ICH4-M/Platform LAN Connect Section ............................................................... 181
Figure 96. Single Solution Interconnect ................................................................................. 182
Figure 97. LAN_CLK Routing Example ................................................................................. 183
Figure 98. Intel 82562ET / Intel 82562EM Termination ......................................................... 185
Figure 99. Critical Dimensions for Component Placement.................................................... 185
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Connector ............................................................................................................... 132
ICH4-M ...................................................................................................................151
GMCH..................................................................................................................... 151
_ /V _ Architecture...................... 172
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Intel 852GM Chipset Platform Design Guide
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