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12.5.3.
12.5.4.
12.5.5.
12.5.6.
12.5.7.
12.5.8.
13.
Reserved, NC, and Test Signals ..............................................................................................233
13.1.
Intel 852GM GMCH RSVD Signals .............................................................................234
14.
Platform Design Checklist ........................................................................................................237
14.1.
General Information .....................................................................................................237
14.2.
Customer Implementation of Voltage Rails .................................................................237
14.3.
Design Checklist Implementation ................................................................................238
14.4.
Mobile Intel Pentium 4 Processor-M and Mobile Intel Celeron Processor ..................239
14.4.1.
14.4.2.
14.4.3.
14.4.4.
14.5.
Intel Celeron M Processor ...........................................................................................244
14.5.1.
14.6.
CK-408 Clock Checklist ...............................................................................................247
14.6.1.
14.7.
Intel 852GM GMCH Checklist......................................................................................249
14.7.1.
14.7.2.
14.7.3.
14.7.4.
14.7.5.
14.7.6.
14.7.7.
14.8.
ICH4-M Checklist .........................................................................................................257
14.8.1.
14.8.2.
14.8.3.
14.8.4.
14.8.5.
®
Intel
852GM Chipset Platform Design Guide
DDR Memory Power Delivery Design Guidelines........................................223
12.5.3.1.
2.5-V Power Delivery Guidelines ..................................................224
12.5.3.2.
GMCH and DDR SMVREF Design Recommendations................224
12.5.3.3.
DDR SMRCOMP Resistive Compensation ..................................225
12.5.3.4.
DDR VTT Termination ..................................................................226
12.5.3.5.
S3/Suspend...................................................................................226
Other GMCH Reference Voltage and Analog Power Delivery ....................226
12.5.4.1.
GMCH GTLVREF..........................................................................226
12.5.4.2.
GMCH AGTL+ I/O Buffer Compensation......................................229
12.5.4.3.
GMCH AGTL+ Reference Voltage................................................229
12.5.4.4.
GMCH Analog Power....................................................................229
ICH4-M Decoupling / Power Delivery Guidelines ........................................231
12.5.5.1.
ICH4-M Decoupling.......................................................................231
Hub Interface Decoupling.............................................................................231
FWH Decoupling ..........................................................................................231
General LAN Decoupling .............................................................................232
Resistor Recommendations.........................................................................239
In Target Probe (ITP) ...................................................................................242
Decoupling Recommendations ....................................................................242
Power-up Sequence.....................................................................................243
Resistor Recommendations.........................................................................244
Resistor Recommendations.........................................................................247
System Memory ...........................................................................................249
14.7.1.1.
GMCH System Memory Interface .................................................249
14.7.1.2.
DDR SO-DIMM Interface ..............................................................250
14.7.1.3.
SODIMM Decoupling Recommendation.......................................251
FSB ..............................................................................................................251
Hub Interface................................................................................................252
Graphics Interfaces ......................................................................................252
14.7.4.1.
LVDS .............................................................................................252
14.7.4.2.
DVO...............................................................................................252
14.7.4.3.
DAC...............................................................................................254
Miscellaneous ..............................................................................................254
GMCH Decoupling Recommendations ........................................................255
GMCH Power-up Sequence ........................................................................256
PCI Interface and Interrupts .........................................................................257
GPIO ............................................................................................................258
AGP_BUSY# Design Requirement..............................................................259
(SMBus) System Management Interface .....................................................259
AC '97 Interface ...........................................................................................260
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