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A
5,15,19..23,27..29,32,36..38,45,51
+V3.3ALWAYS
C7A2
0.1UF
U7A3
1
45
PWR_PWROK
74AHC1G08
2
20
V1.5_PWRGD
5,15,19..23,27..29,32,36..38,45,51
+V3.3ALWAYS
4
C7B1
0.1UF
U7B1
1
44
DDR_VR_PWRGD
74AHC1G08
2
21
V5A_PWRGD
5,15,19..23,27..29,32,36..38,45,51
C4B2
0.1UF
40
ON_BOARD_VR_PWRGD
INTERPOSER_PRES#
3
5,15,19..23,27..29,32,36..38,45,51
14
U4B3C
10
INTERPOSER_PRES
74HC00
8
13
9
12
7
R4N3
100K
2
J5C1
1
2
OFF_BOARD_VR_ON
3
4
SC_PSI
5
6
7
8
9
10
11
12
+V3.3S
13
14
15
16
+V5S
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
1
37
38
39
40
20x2_Header
Connector 1
(rows A,B)
A
B
Step 1 - Power OK
C7A4
0.1UF
U7A5
MAIN_PWROK
4
1
4
PM_PWROK 19,21,25,32,37
MAIN2_PWROK
74AHC1G08
2
4
+V3.3ALWAYS
3,5,6,8,9,11,15..18,20,21,23,26,31,33..36,38,40,43,45,51
VR PWRGD CIRCUIT
14
U4B3A
14
U4B3B
1
PWRGD1
74HC00
3
4
74HC00
2
6
5
7
7
+V3.3ALWAYS
14
U4B3D
74HC00
PWRGD2
11
7
Steelcliff Headers
PM_STPCPU# 6,19,37,40
40
PM_DPRSLPVR 19,37,40
40
R5C4
PM_PSI#
3,40
40
0
3,5,6,8,9,11,15..18,20,21,23,26,31,33..36,38,40,43,45,51
INTERPOSER_PRES#
8,15..18,20,23..25,27,34,35,38,40,41,43,45,46
+V5S
+VDC
16,21,41,43,45
VR Interposer Headers
B
C
Step 2 - VR ON
3,5,6,8,9,11,15..18,20,21,23,26,31,33..36,38,40,43,45,51
43
CORE_VR_ON
32
VR_SHUT_DOWN#
Step 3 - Power Good
3,5,6,8,9,11,15..18,20,21,23,26,31,33..36,38,40,43,45,51
+V3.3S
+V3.3S
R6C10
R6C4
C6C6
1.58K
10K
0.1UF
VDD+
1%
OPAMP_N
2
-
TLV2463
VR_PWRGD 7,37
OPAMP_P
3
2
+
C6C4
1
1uF
R6C6
Q6C1
20%
2K_1%
BSS84
3
3,5,6,8,9,11,15..18,20,21,23,26,31,33..36,38,40,43,45,51
8,15..18,20,23..25,27,34,35,38,40,41,43,45,46
+V5S
R1G6
8.2K
46
IMVP-4Strap_VID1
46
IMVP-4Strap_VID2
46
IMVP-4Strap_VID3
46
IMVP-4Strap_VID4
46
IMVP-4Strap_VID5
J5C2
1
2
VR_VID0
VR_VID3
40
3
4
VR_VID1
VR_VID4
40
5
6
VR_VID2
VR_VID5
40
7
8
+V3.3S
9
10
11
12
+V3.3S 3,5,6,8,9,11,15..18,20,21,23,26,31,33..36,38,40,43,45,51
13
14
15
16
+V5S
8,15..18,20,23..25,27,34,35,38,40,41,43,45,46
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
20x2_Header
Connector 2
(rows C,D)
C
D
3,5,6,8,9,11,15..18,20,21,23,26,31,33..36,38,40,43,45,51
+V3.3S
C4B5
0.1UF
U4B4
INTERPOSER_PRES#
1
4
2
74AHC1G08
OFF_BOARD_VR_ON
R2G13
R6C9
10
10K
10K
U6C1A
1
DELAYED_VR_PWRGD 19,37
OPAMP_EN
5
GND
4
+V3.3S
R1G7
R1G8
R1G9
R1G10
R1G11
R1H3
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
IMVP-4Strap_VID0
J1H1
4
H_VID0
4
H_VID1
2X8_HDR
4
H_VID2
4
H_VID3
4
H_VID4
4
H_VID5
8,15..18,20,23..25,27,34,35,38,40,41,43,45,46
+V5S
R1G5
10K
MUX_SWITCH
Title
Processor VR Interposer Support & Power Circuitry
Size
Project:
A
Intel Celeron M / 852GM CRB
Date:
Wednesday, January 12, 2005
D
E
+V3.3S
C4B6
0.1UF
R4N2
2.2k
U4B5
1
4
ON_BOARD_VR_ON 40,41
2
74AHC1G08
3,5,6,8,9,11,15..18,20,21,23,26,31,33..36,38,40,43,45,51
+V3.3S
R3G11
10K
VR_PWRGD_CK408# 6,40
3
IMVP_PWRGD_D
Q2G1
1
2N3904
2
Note: J1H1 enables
Manual VID strapping
With pin 13 high, B input goes to C
output. With pin 13 low, A input goes
to C output.
Input
Output
S2
S1
S0
A
C
1
1
0
B
C
1
1
1
U1G1
2
46
VR_VID0
A0
C0
5
44
VR_VID1
A1
C1
8
41
VR_VID2
A2
C2
11
38
A3
C3
VR_VID3
13
36
A4
C4
VR_VID4
16
33
VR_VID5
A5
C5
18
31
A6
C6
21
28
A7
C7
23
26
A8
C8
3
45
B0
D0
6
43
B1
D1
9
40
B2
D2
12
37
B3
D3
14
35
B4
D4
17
32
B5
D5
19
30
B6
D6
22
27
B7
D7
+V5S
24
25
B8
D8
1
7
S0
VCC
48
4
S1
GND0
S2_S1
47
10
S2
GND1
C1G1
34
15
GND5
GND2
39
20
GND6
GND3
0.01UF
42
29
GND7
GND4
74CBT16209A
Document Number
Rev
C26116
4.403
Sheet
39
of
51
E
4
3
40
40
40
40
2
40
40
1
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