Intel 852GM Design Manual page 14

Tables
Table 1. Front Side Bus Routing Summary for the Processor................................................. 31
Table 2. Processor Front Side Bus Data Signal Routing Guidelines....................................... 35
Table 3. Processor Front Side Bus Address Signal Routing Guidelines................................. 35
Table 4. Processor Front Side Bus Control Signal Routing Guidelines .................................. 39
Table 5. Layout Recommendations for Topology 1A............................................................... 40
Table 6. Layout Recommendations for Topology 1B............................................................... 41
Table 7. Layout Recommendations for Topology 1C .............................................................. 42
Table 8. Layout Recommendations for Topology 2A............................................................... 43
Table 9. Layout Recommendations for Topology 2B............................................................... 43
Table 10. Layout Recommendations for Topology 2C ............................................................ 44
Table 11. Layout Recommendations for Topology 3 ............................................................... 45
Table 12. Mobile Intel Pentium 4 Processor-M and Intel 852GM Chipset Package Lengths.. 46
Table 13. FSB Common Clock Signal Internal Layer Routing Guidelines .............................. 54
Table 14. Processor and GMCH FSB Common Clock Signal Package Lengths and Minimum
Table 15. Processor FSB Data Source Synchronous Signal Trace Length Mismatch
Table 16. FSB Source Synchronous Data Signal Routing Guidelines .................................... 60
Table 17. Processor FSB Address Source Synchronous Signal Trace Length Mismatch
Table 18. Processor FSB Source Synchronous Address Signal Routing Guidelines ............. 61
Table 19. Intel Celeron M Processor and GMCH Source Synchronous FSB Signal Package
Table 20. Asynchronous AGTL+ Nets ..................................................................................... 64
Table 21. Layout Recommendations for Topology 1A............................................................. 65
Table 22. Layout Recommendations for Topology 1B............................................................. 66
Table 23. Layout Recommendations for Topology 1C ............................................................ 67
Table 24. Layout Recommendations for Topology 2A............................................................. 68
Table 25. Layout Recommendations for Topology 2B............................................................. 68
Table 26. Layout Recommendations for Topology 2C ............................................................ 69
Table 27. Layout Recommendations for Topology 3 ............................................................... 70
Table 28. Processor RESET# Signal Routing Guidelines with ITP700FLEX Connector ........ 72
Table 29. ITP Signal Default Strapping When ITP Debug Port Not Used ............................... 80
Table 30. Intel 852GM GMCH Chipset DDR Signal Groups ................................................... 83
Table 31. Length Matching Formulas ...................................................................................... 84
Table 32. Clock Signal Mapping .............................................................................................. 85
Table 33. Clock Signal Group Routing Guidelines .................................................................. 86
Table 34. DDR Clock Package Lengths .................................................................................. 89
Table 35. Data Signal Group Routing Guidelines.................................................................... 93
Table 36. SDQ/SDM to SDQS Mapping .................................................................................. 96
Table 37. DDR SDQ/SDM/SDQS Package Lengths ............................................................... 98
Table 38. Control Signal to SO-DIMM Mapping .................................................................... 101
Table 39. Control Signal Routing Guidelines......................................................................... 102
Table 40. Control Group Package Lengths ........................................................................... 106
Table 41. Command Topology 1 Routing Guidelines ............................................................ 108
Table 42. Command Topology 2 Routing Guidelines ............................................................ 112
Table 43. Command Topology 3 Routing Guidelines ............................................................ 117
Table 44. Command Group Package Lengths ...................................................................... 120
Table 45. CPC Signal to SO-DIMM Mapping ........................................................................ 121
Table 46. CPC Signal Routing Guidelines ............................................................................. 122
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Board Trace Lengths ................................................................................................ 55
Mapping .................................................................................................................... 59
Mapping .................................................................................................................... 60
Lengths ..................................................................................................................... 62
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Intel 852GM Chipset Platform Design Guide
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