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A
22..24
PCI_AD[31:0]
PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
4
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
3
PCI_AD31
22..24
PCI_C/BE0#
22..24
PCI_C/BE1#
22..24
PCI_C/BE2#
22..24
PCI_C/BE3#
TP_GNT0#
22
PCI_GNT1#
22
PCI_GNT2#
23
PCI_GNT3#
24
PCI_GNT4#
21
PCI_REQ0#
21,22
PCI_REQ1#
21,22
PCI_REQ2#
21,23
PCI_REQ3#
21,24
PCI_REQ4#
6
CLK_ICHPCI
21..24
PCI_DEVSEL#
21..24
PCI_FRAME#
22,23
PCI_REQA#
2
24
PCI_REQB#
19,22,23
PCI_GNTA#
24
PCI_GNTB#
21..24
PCI_IRDY#
22..24
PCI_PAR
21..23
PCI_PERR#
21..24
PCI_LOCK#
15,22,23,37
PCI_PME#
21..24
PCI_SERR#
21..24
PCI_STOP#
21..24
PCI_TRDY#
7,8,10,15,33
PCI_RST#
1
C8G2
0.1UF
22..24,26,31,32,34,37
BUF_PCI_RST#
A
B
U7G2A
SM_INTRUDER#
H5
PCI_AD0
SMLINK0
J3
PCI_AD1
SMLINK1
H3
PCI_AD2
SMB_CLK
K1
PCI_AD3
SMB_DATA
G5
PCI_AD4
SMB_ALERT#/GPIO11
J4
PCI_AD5
H4
PCI_AD6
CPU_A20GATE
J5
PCI_AD7
CPU_A20M#
K2
ICH4-M
PCI_AD8
CPU_DPSLP#
G2
PCI_AD9
CPU_FERR#
L1
PCI_AD10
CPU_IGNNE#
PART A
G4
PCI_AD11
CPU_INIT#
L2
PCI_AD12
CPU_INTR
H2
PCI_AD13
CPU_NMI
L3
PCI_AD14
CPU_PWRGOOD
F5
PCI_AD15
CPU_RCIN#
F4
PCI_AD16
CPU_SLP#
N1
PCI_AD17
CPU_SMI#
E5
PCI_AD18
CPU_STPCLK#
N2
PCI_AD19
E3
PCI_AD20
HUB_PD0
N3
PCI_AD21
HUB_PD1
E4
PCI_AD22
HUB_PD2
M5
PCI_AD23
HUB_PD3
E2
PCI_AD24
HUB_PD4
P1
PCI_AD25
HUB_PD5
E1
PCI_AD26
HUB_PD6
P2
PCI_AD27
HUB_PD7
D3
PCI_AD28
HUB_PD8
R1
PCI_AD29
HUB_PD9
PCI
D2
PCI_AD30
HUB_PD10
P4
I/F
PCI_AD31
HUB_PD11
HUB_CLK
J2
PCI_C/BE0#
K4
PCI_C/BE1#
HUB_PSTRB#
M4
PCI_C/BE2#
HUB_PSTRB
N4
PCI_C/BE3#
HUB_RCOMP
HUB_VREF
C1
PCI_GNT0#
HUB_VSWING
E6
PCI_GNT1#
A7
PCI_GNT2#
INT_APICCLK
B7
PCI_GNT3#
INT_APICD0
D6
PCI_GNT4#
INT_APICD1
INT_PIRQA#
B1
PCI_REQ0#
INT_PIRQB#
A2
PCI_REQ1#
INT_PIRQC#
B3
PCI_REQ2#
INT_PIRQD#
C7
PCI_REQ3#
INT_PIRQE#/GPIO2
B6
PCI_REQ4#
INT_PIRQF#/GPIO3
INT_PIRQG#/GPIO4
P5
PCI_CLK
INT_PIRQH#/GPIO5
M3
PCI_DEVSEL#
INT_IRQ14
F1
PCI_FRAME#
INT_IRQ15
B5
PCI_GPIO0/REQA#
INT_SERIRQ
A6
PCI_GPIO1/REQB_L/REQ5#
E8
PCI_GPIO16/GNTA#
EEP_CS
C5
PCI_GPIO17/GNTB_L/GNT5#
EEP_DIN
L5
PCI_IRDY#
EEP_DOUT
G1
PCI_PAR
EEP_SHCLK
L4
PCI_PERR#
M2
PCI_LOCK#
LAN_RXD0
W2
PCI_PME#
LAN_RXD1
U5
PCI_RST#
LAN_RXD2
K5
PCI_SERR#
LAN_TXD0
F3
PCI_STOP#
LAN_TXD1
F2
PCI_TRDY#
LAN_TXD2
LAN_JCLK
LAN_RSTSYNC
LAN_RST#
ICH4-M
+V3.3
15,19,20,23,27,30,32,35,37,38,44,45
U8G1
1
4
74AHC1G08
2
Buffer to reduce loading on PCI_RST#
B
C
3..5,9,19,20,40,42,43,46
+VCCP
W6
SM_INTRUDER# 21,37
AC3
AB1
SMB_CLK
AC4
SMB_DATA
AB4
AA5
SMB_ALERT# 21,37
H_A20GATE 36
Y22
CPU_A20M#
R6W21
0
AB23
CPU_DPSLP#
R6H16
0
U23
CPU_FERR#
R6W18
56
AA21
CPU_IGNNE#
R6W16
0
W21
CPU_INIT#
V22
CPU_INTR
R6W17
0
AB22
CPU_NMI
R6H14
0
V21
CPU_PWRGOOD
R6W20
0
Y23
U22
CPU_SLP#
R6W14
0
U21
CPU_SMI#
R6H12
0
W23
CPU_STPCLK#
R6W15
0
V23
HUB_PD[10:0] 8,10
HUB_PD0
L19
HUB_PD1
L20
HUB_PD2
R6H13
NO_STUFF_0
M19
HUB_PD3
M21
HUB_PD4
P19
HUB_PD5
R19
HUB_PD6
T20
HUB_PD7
PLACE RCOMP resistor within
R20
HUB_PD8
P23
0.5" of ICH pad using a 10 mil
HUB_PD9
L22
trace w/ 20 mil spacing
HUB_PD10
N22
HUB_PD11
R6H1
56
RCOMP R should be 2/3
K21
T21
board impedance
CLK_ICH66 6
N20
HUB_PSTRB# 8,10
P21
HUB_PSTRB 8,10
HUB_RCOMP_ICH
R23
HUB_VREF_ICH
M23
HUB_VSWING_ICH
R22
INT_APICCLK
J19
INT_APICD0
H19
INT_APICD1
K20
D5
INT_PIRQA# 15,21,23,24
C2
INT_PIRQB# 15,21,23,24
B4
INT_PIRQC# 21,23,24
A3
INT_PIRQD# 21,23,24
INT_PIRQE#_D
R7F11
0
C8
INT_PIRQE# 21..23
INT_PIRQF#_D
R7F10
0
D7
INT_PIRQF# 21..23
INT_PIRQG#_D
R7F3
0
C3
INT_PIRQG# 21..23
INT_PIRQH#_D
R7G3
0
C4
INT_PIRQH# 21..23,37
AC13
INT_IRQ14 21,26,37
AA19
INT_IRQ15 21,26,37
J22
INT_SERIRQ 22..24,32,34,37
U7G1
EEP_CS
D10
1
CS
VCC
EEP_SK
D11
2
SK
DC
A8
3
DI
ORG
EEP_DIN
C12
4
DO
GND
AT88SC153
A10
LAN_RXD0 30
A9
LAN_RXD1 30
EEPROM for ICH4-M LAN
A11
LAN_RXD2 30
B10
(Atmel AT93C66-10PC-2.7)
LAN_TXD0 30
C10
LAN_TXD1 30
EEP_DOUT 19
A12
LAN_TXD2 30
C11
LAN_JCLK 30
B11
LAN_RST 30
Y5
PM_LANPWROK 30,32
21..24,46
R9Y1
6,8,11,12,16
10K
INT_APICCLK
INT_APICD0
INT_APICD1
R6W2
R6W8
R6W5
0
10K
10K
C
D
3,5,6,8,9,11,15..17,20,21,23,26,31,33..36,38..40,43,45,51
R6W19
56
H_A20M# 3
H_DPSLP# 3,7,37
H_FERR# 3
H_IGNNE# 3
H_INIT#_D
R6H15
330
H_INTR 3,37
H_NMI
3,37
H_PWRGD 3,37
R6J1
0
H_RCIN# 32,37
H_CPUSLP# 3,37
H_SMI# 3,37
H_STPCLK# 3,37
Layout Note: R6H12 will
share path with R6H13
PSMI#
46
+V1.5S_ICHHUB
20
R6H3
48.7_1%
0.01UF
+V1.5S_ICHHUB
R6W12
130_1%
C6W7
C6W5
R6W13
0.01UF
0.1UF
150_1%
+V3.3_ICHLAN
20
C7G1
8
7
0.1UF
6
5
8,15..17,20,23..25,27,34,35,38..41,43,45,46
U6G1
1
SMB_S_OE1#
OE1#
VCC
2
SMB_CLK
1A
OE2#
3
SMB_CLK_S
1B
2B
4
GND
2A
R6G4
74CBT3306
100
Title
ICH4-M (1 of 3)
Size
Project:
A
Intel Celeron M / 852GM CRB C26116
Date:
Wednesday, January 12, 2005
D
E
+V3.3S
R8G8
R8G7
1.3K
330
5%
6
FWH_INIT# 31
CR8G2B
2
3904
1
3
CR8G2A
5
3904
4
H_INIT#
3,37
+V1.5S_ICHHUB
20
R6W10
487_1%
HUB_VREF_ICH
46
C6W3
R6W9
C6W4
0.1UF
150_1%
HUB_VREF and HUB_VSWING
20
circuits for internal
testing need 10 mil traces
w/ 20 mil spacing
HUB INTERFACE VSWING VOLTAGE
HUB INTERFACE LAYOUT:
Route signals with 4/8 trace/space routing. Signals
must match +/- 0.1" of HUB_STB/STB# signals
+V5S
This Bus Switch prevents
leakage of the SMBus into
C6F3
devices powered on the
0.1UF
switched rail.
8
7
SMB_S_OE2#
6
SMB_DATA_S 6,8,11,12,16
5
SMB_DATA 21..24,46
R6G2
100
Document Number
Rev
4.403
Sheet
18
of
51
E
4
3
2
1
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