Table of Contents
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A
13
M_DATA[63:0]
M_DATA0
AF2
M_DATA1
AE3
M_DATA2
AF4
M_DATA3
AH2
M_DATA4
AD3
M_DATA5
AE2
M_DATA6
AG4
4
M_DATA7
AH3
M_DATA8
AD6
M_DATA9
AG5
M_DATA10
AG7
M_DATA11
AE8
M_DATA12
AF5
M_DATA13
AH4
M_DATA14
AF7
M_DATA15
AH6
M_DATA16
AF8
M_DATA17
AG8
M_DATA18
AH9
M_DATA19
AG10
M_DATA20
AH7
M_DATA21
AD9
M_DATA22
AF10
M_DATA23
AE11
M_DATA24
AH10
M_DATA25
AH11
M_DATA26
AG13
M_DATA27
AF14
M_DATA28
AG11
M_DATA29
AD12
M_DATA30
AF13
M_DATA31
AH13
3
M_DATA32
AH16
M_DATA33
AG17
M_DATA34
AF19
M_DATA35
AE20
M_DATA36
AD18
M_DATA37
AE18
M_DATA38
AH18
M_DATA39
AG19
M_DATA40
AH20
M_DATA41
AG20
M_DATA42
AF22
M_DATA43
AH22
M_DATA44
AF20
M_DATA45
AH19
M_DATA46
AH21
M_DATA47
AG22
M_DATA48
AE23
M_DATA49
AH23
M_DATA50
AE24
M_DATA51
AH25
M_DATA52
AG23
M_DATA53
AF23
M_DATA54
AF25
M_DATA55
AG25
M_DATA56
AH26
2
M_DATA57
AE26
M_DATA58
AG28
M_DATA59
AF28
M_DATA60
AG26
M_DATA61
AF26
M_DATA62
AE27
M_DATA63
AD27
13
M_CB[7:0]
M_CB0
AG14
M_CB1
AE14
M_CB2
AE17
M_CB3
AG16
M_CB4
AH14
M_CB5
AE15
M_CB6
AF16
M_CB7
AF17
AJ24
44
SM_VREF_MCH
C5F13
0.1UF
1
A
B
U5E1E
M_DQS0
AG2
SDQ0
SDQS0
M_DQS1
AH5
SDQ1
SDQS1
M_DQS2
AH8
SDQ2
SDQS2
M_DQS3
AE12
SDQ3
SDQS3
M_DQS4
AH17
SDQ4
SDQS4
M_DQS5
AE21
SDQ5
SDQS5
M_DQS6
AH24
SDQ6
SDQS6
M_DQS7
AH27
SDQ7
SDQS7
M_DQS8
AD15
SDQ8
SDQS8
SDQ9
M_AA0
AC18
SDQ10
SMA_A0
M_AA1
AD14
SDQ11
SMA_A1
M_AA2
AD13
SDQ12
SMA_A2
M_AA3
AD17
SDQ13
SMA_A3
M_AA4
AD11
SDQ14
SMA_A4
M_AA5
AC13
SDQ15
SMA_A5
M_AA6
AD8
SDQ16
SMA_A6
M_AA7
AD7
SDQ17
SMA_A7
M_AA8
AC6
SDQ18
SMA_A8
M_AA9
AC5
SDQ19
SMA_A9
M_AA10
AC19
SDQ20
SMA_A10
M_AA11
AD5
SDQ21
SMA_A11
M_AA12
AB5
SDQ22
SMA_A12
SDQ23
M_AB1
AD16
SDQ24
SMA_B1
M_AB2
AC12
SDQ25
SMA_B2
M_AB4
AF11
SDQ26
SMA_B4
M_AB5
AD10
SDQ27
SMA_B5
SDQ28
AC7
SDQ29
SCKE0
AB7
SDQ30
SCKE1
AC9
SDQ31
SCKE2
AC10
SDQ32
SCKE3
AD23
SDQ33
SCS0#
AD26
SDQ34
SCS1#
AC22
SDQ35
SCS2#
AC25
SDQ36
SCS3#
SDQ37
AD22
SDQ38
SBA0
AD20
SDQ39
SBA1
SDQ40
AC21
SDQ41
SRAS#
AC24
SDQ42
SCAS#
AD25
SDQ43
SWE#
SDQ44
AB2
SDQ45
SCMDCLK0
AA2
SDQ46
SCMDCLK0#
AC26
SDQ47
SCMDCLK1
AB25
SDQ48
SCMDCLK1#
AC3
SDQ49
SCMDCLK2
AD4
SDQ50
SCMDCLK2#
AC2
SDQ51
SCMDCLK3
AD2
SDQ52
SCMDCLK3#
AB23
SDQ53
SCMDCLK4
AB24
SDQ54
SCMDCLK4#
AA3
SDQ55
SCMDCLK5
AB4
SDQ56
SCMDCLK5#
SDQ57
M_DM0
AE5
SDQ58
SDM0
M_DM1
AE6
SDQ59
SDM1
M_DM2
AE9
SDQ60
SDM2
M_DM3
AH12
SDQ61
SDM3
M_DM4
AD19
SDQ62
SDM4
M_DM5
AD21
SDQ63
SDM5
M_DM6
AD24
SDQ64
SDM6
M_DM7
AH28
SDQ65
SDM7
M_DM8
AH15
SDQ66
SDM8
Layout note: Route to
SDQ67
vias near ball
SDQ68
TP_M_RCVO#
AC15
SDQ69
SRCVENOUT#
TP_M_RCVI#
AC16
SDQ70
SRCVENIN#
SDQ71
AB1
SMRCOMP
AJ22
SMVREF
SMVSWINGL
AJ19
SMVSWINGH
Intel 852GM Skt
C5F6
C5F5
0.1UF
0.1UF
B
C
M_DQS[8:0] 13
15
DVOBD[11:0]
M_AA0
12..14
8,9,51
+V1.5S_GMCH_DVO
M_AA[2:1] 11,14
R6E3
M_AA3
12..14
15
DVOBCLK
100K
15
DVOBCLK#
15
DVOBHSYNC
M_AA[5:4] 11,14
15
DVOBVSYNC
15
DVOBBLANK#
15
DVOBFLDSTL
15
DVOBCINTRB
15
DVOBCCLKINT
15
DVOCD[11:0]
R6E5
M_AA[12:6] 12..14
100K
M_AB[2:1] 12,14
M_AB[5:4] 12,14
M_CKE0
11,12,14
M_CKE1
11,12,14
M_CKE2
12,14
M_CKE3
12,14
M_CS0#
11,12,14
M_CS1#
11,12,14
M_CS2#
12,14
M_CS3#
12,14
15
DVOCCLK
15
DVOCCLK#
M_BS0#
12..14
15
DVOCHSYNC
M_BS1#
12..14
15
DVOCVSYNC
15
DVOCBLANK#
M_RAS#
12..14
15
DVOCFLDSTL
M_CAS#
12..14
R6D2
M_WE#
12..14
15
MI2CCLK
100K
15
MI2CDATA
M_CLK_DDR0 11
15
MDVICLK
15
MDVIDATA
M_CLK_DDR0# 11
M_CLK_DDR1 11
15
MDDCCLK
15
MDDCDATA
M_CLK_DDR1# 11
M_CLK_DDR2 11
15
ADDID[7:0]
M_CLK_DDR2# 11
M_CLK_DDR3 12
M_CLK_DDR3# 12
M_CLK_DDR4 12
M_CLK_DDR4# 12
M_CLK_DDR5 12
M_CLK_DDR5# 12
M_DM[8:0] 13
8,15
ADDDETECT
15
DPMS_CLK
15,46
DVO_VREF
Place C6E1 near
C6E1
19,51
AGP_BUSY#
GMCH
0.1UF
10
MCH_GRCOMP
6
CLK_MCH66
RSVD0
RSVD1
RSVD2
RSVD3
RSVD4
MCH_SMRCOMP 10
8,15
AGP_ST2
MCH_SMVSWINGL 10
8,15
AGP_ST1
MCH_SMVSWINGH 10
8,15
AGP_ST0
RSVD8
RSVD9
RSVD11
C
D
U5E1B
DVOBD0
R3
DVOBD0
BLUE
DVOBD1
R5
DVOBD1
BLUE#
DVOBD2
R6
DVOBD2
GREEN
DVOBD3
R4
DVOBD3
GREEN#
DVOBD4
P6
DVOBD4
DVOBD5
P5
DVOBD5
RED#
DVOBD6
N5
DVOBD6
HSYNC
DVOBD7
P2
DVOBD7
VSYNC
DVOBD8
N2
DVOBD8
DVOBD9
N3
DVOBD9
REFSET
DVOBD10
M1
DVOBD10
DVOBD11
M5
DVOBD11
DDCACLK
DDCADATA
P3
DVOBCLK
P4
DVOBCLK#
T6
DVOBHSYNC
IYAM0
T5
DVOBVSYNC
IYAM1
L2
DVOBBLANK#
IYAM2
M2
DVOBFLDSTL
IYAM3
IYAP0
G2
DVOBCINTRB
IYAP1
M3
DVOBCCLKINT
IYAP2
IYAP3
DVOCD0
K5
DVOCD0
IYBM0
DVOCD1
K1
DVOCD1
IYBM1
DVOCD2
K3
DVOCD2
IYBM2
R6E6
DVOCD3
K2
DVOCD3
IYBM3
100K
DVOCD4
J6
DVOCD4
IYBP0
DVOCD5
J5
DVOCD5
IYBP1
DVOCD6
H2
DVOCD6
IYBP2
DVOCD7
H1
DVOCD7
IYBP3
DVOCD8
H3
DVOCD8
ICLKAM
DVOCD9
H4
DVOCD9
ICLKAP
DVOCD10
H6
DVOCD10
ICLKBM
DVOCD11
G3
DVOCD11
ICLKBP
J3
DVOCCLK
DDCPCLK
J2
DVOCCLK#
DDCPDATA
K6
DVOCHSYNC
L5
DVOCVSYNC
PANELBKLTCTL
L3
DVOCBLANK#
PANELBKLTEN
H5
DVOCFLDSTL
PANELVDDEN
K7
MI2CCLK
LVREFH
N6
MI2CDATA
LVREFL
N7
MDVICLK
M6
MDVIDATA
LVBG
P7
MDDCCLK
T7
MDDCDATA
ADDID0
E5
ADDID0
DREFCLK
ADDID1
F5
ADDID1
DREFSSCLK
ADDID2
E3
ADDID2
LCLKCTLA
ADDID3
E2
ADDID3
LCLKCTLB
ADDID4
G5
ADDID4
ADDID5
F4
ADDID5
ADDID6
G6
ADDID6
DPWR#
ADDID7
F6
ADDID7
DPSLP#
L7
ADDDETECT
RSTIN#
D5
DPMS
PWROK
F1
GVREF
EXTTS0
F7
AGPBUSY#
MCHDETECTVSS
D1
GRCOMP
Y3
66IN
AA5
RVSD0
F2
RVSD1
F3
RVSD2
B2
RVSD3
B3
RVSD4
C2
RVSD5
C3
RVSD6
C4
RVSD7
D2
RVSD8
NC10
D3
RVSD9
NC11
TP_RSVD10
D7
RVSD10
L4
RVSD11
Intel 852GM Skt
Title
Intel 852GM GMCH (1 of 3)
Size
Project:
A
Intel Celeron M / 852GM CRB
Date:
Wednesday, January 12, 2005
D
E
C9
DAC_BLUE 17
D9
C8
DAC_GREEN 17
D8
A7
DAC_RED 17
RED
A8
H10
DAC_HSYNC 17
J9
DAC_VSYNC 17
E8
DAC_REFSET 10
B6
DAC_DDCACLK 17,24
G9
DAC_DDCADATA 17,24
G14
LVDS_YAM0 16
E15
LVDS_YAM1 16
C15
LVDS_YAM2 16
C13
LVDS_YAM3 16
F14
LVDS_YAP0 16
E14
LVDS_YAP1 16
C14
LVDS_YAP2 16
B13
LVDS_YAP3 16
H12
LVDS_YBM0 16
E12
LVDS_YBM1 16
C12
LVDS_YBM2 16
G11
LVDS_YBM3 16
G12
LVDS_YBP0 16
E11
LVDS_YBP1 16
C11
LVDS_YBP2 16
G10
LVDS_YBP3 16
D14
LVDS_CLKAM 16
E13
LVDS_CLKAP 16
E10
LVDS_CLKBM 16
F10
LVDS_CLKBP 16
B4
LVDS_DDCPCLK 16
C5
LVDS_DDCPDATA 16
G8
LVDS_BKLTCTL 16
F8
LVDS_BKLTEN 16
A5
LVDS_VDDEN 16
TP_LVDS_REFH
D12
TP_LVDS_REFL
F12
LVDS_LVBG
No Stuff
B12
J5C3
A10
LIBG
LVDS_LIBG 8
B7
DREFCLK 6
B17
DREFSSCLK 6
H9
LCLKCTLA 6,16
C6
LCLKCTLB 6,8,16
AA22
H_DPWR# 3
Y23
H_DPSLP# 3,18,37
AD28
PCI_RST# 8,10,15,18,33
J11
VR_PWRGD 37,39
D6
MCH_EXTTS0 8
AJ1
MCH_DETECT# 51
TP_MCH_NC0
B1
NC0
AH1
TP_MCH_NC1 51
NC1
TP_MCH_NC2
A2
NC2
AJ2
NC3
TP_MCH_NC3 51
TP_MCH_NC4
A28
NC4
TP_MCH_NC5
AJ28
NC5
TP_MCH_NC6
A29
NC6
TP_MCH_NC7
B29
NC7
TP_MCH_NC8
AH29
NC8
TP_MCH_NC9
AJ29
NC9
TP_MCH_NC10
AA9
TP_MCH_NC11
AJ4
Document Number
Rev
C26116
4.403
Sheet
7
of
51
E
4
3
2
1
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