Intel 852GM Design Manual page 6

8.2.2.
8.3. Digital Video Out Port.................................................................................................. 138
8.3.1.
8.3.2.
8.4. DVO GMBUS and DDC Interface Considerations ...................................................... 141
8.4.1.
8.5. Miscellaneous Input Signals and Voltage Reference.................................................. 142
9. Hub Interface............................................................................................................................ 145
9.1. Hub Interface Compensation ...................................................................................... 145
9.2. Hub Interface Data HL[10:0] and Strobe Signals........................................................ 146
9.2.1.
9.2.2.
9.3. Hub VREF/VSWING Generation/Distribution ............................................................. 148
9.3.1.
9.3.2.
9.3.3.
9.4. Hub Interface Decoupling Guidelines.......................................................................... 152
10. I/O Subsystem.......................................................................................................................... 153
10.1. IDE Interface................................................................................................................ 153
10.1.1.
10.1.2.
10.1.3.
10.1.4.
10.2. PCI............................................................................................................................... 158
10.3. AC'97........................................................................................................................... 158
10.3.1.
10.3.2.
10.3.3.
10.4. USB 2.0 Guidelines and Recommendations............................................................... 164
10.4.1.
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8.2.1.1. Package Length Compensation ................................................... 136
LVDS Routing Guidelines............................................................................ 136
DVO Interface Signal Groups ...................................................................... 138
8.3.1.1. DVOC Interface Signals ............................................................... 138
DVO Port Interface Routing Guidelines....................................................... 139
8.3.2.1. Length Mismatch Requirements................................................... 139
8.3.2.2. Package Length Compensation ................................................... 139
8.3.2.3. DVO Routing Guidelines .............................................................. 140
8.3.2.4. DVO Port Termination .................................................................. 141
Leaving the DVO Port Unconnected ........................................................... 142
HL[10:0] and Strobe Signals Internal Layer Routing ................................... 146
Terminating HL[11] ...................................................................................... 148
Single Generation Voltage Reference Divider Circuit ................................. 148
Locally Generated Voltage Reference Divider Circuit................................. 149
9.3.2.1. ICH4-M Single Generated Voltage Reference Divider Circuit ..... 149
9.3.2.2. GMCH Single Generated Voltage Reference Divider Circuit....... 150
Separate GMCH and ICH4-M Voltage Divider Circuits for VREF and
VSWING ...................................................................................................... 150
9.3.3.1. Separate ICH4-M Voltage Divider Circuits for HIVREF and
HI_VSWING.................................................................................. 150
9.3.3.2. Separate GMCH Voltage Divider Circuits for HLVREF and
PSWING ....................................................................................... 151
Cabling......................................................................................................... 153
Primary IDE Connector Requirements ........................................................ 154
Secondary IDE Connector Requirements ................................................... 155
Mobile IDE Swap Bay Support .................................................................... 155
10.1.4.1. ICH4-M IDE Interface Tri-State Feature....................................... 156
10.1.4.2. S5/G3 to S0 Power-Up Procedures for IDE Swap Bay................ 157
10.1.4.3. Power Down Procedures for Mobile Swap Bay ........................... 157
10.1.4.4. Power-Up Procedures After Device "Hot" Swap Completed........ 157
AC'97 Routing.............................................................................................. 162
Motherboard Implementation....................................................................... 163
10.3.2.1. Valid Codec Configurations .......................................................... 163
SPKR Pin Configuration .............................................................................. 163
Layout Guidelines ........................................................................................ 164
10.4.1.1. General Routing and Placement .................................................. 164
10.4.1.2. USB 2.0 Trace Separation............................................................ 165
10.4.1.3. USBRBIAS Connection ................................................................ 165
10.4.1.4. USB 2.0 Termination .................................................................... 166
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Intel 852GM Chipset Platform Design Guide
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