HP 64767 User Manual page 205

Predefined Values for Qualifiers When you specify status qualifiers for
analyzer states (by pressing the status softkey), you will be given the following
softkeys which are predefined values for the qualifiers.
Qualifier Status Bits (31..20)
bus 01xxx xxxx xxxxb
coproc 01xxx xxxx xxxxb
dma 01xxx x1xx xxxxb
dmaior 01xxx x1xx 1001b
dmaiow 01xxx x1xx 1010b
dmamr 01xxx x1xx 1101b
dmamw 01xxx x1xx 1110b
exec 00xxx xxxx xxxxb
grd 01xxx 0xxx xxxxb
halt 01xxx xxxx 1011b
intack 01xxx xxxx 1000b
ioread 01xxx xxxx 1001b
iowrite 01xxx xxxx 1010b
memread 01xxx xxxx 1101b
memwrite 01xxx xxxx 1110b
mon 0x0xx xxxx xxxxb
opcode 01xxx xxxx 1100b
proc 01xxx x0xx xxxxb
prochalt 01xxx x0xx 1011b
procinta 01xxx x0xx 1000b
procior 01xxx x0xx 1001b
prociow 01xxx x0xx 1010b
procmr 01xxx x0xx 1101b
procmw 01xxx x0xx 1110b
procopf 01xxx x0xx 1100b
procr 01xxx x0xx 1x01b
procw 01xxx x0xx 1x10b
rom 01xx0 xxxx xxxxb
usr 0x1xx xxxx xxxxb
These predefined values may be used as other values would be used. For example:
trace after status memwrite
is the same as:
trace after status 01xxxxxxx1110b
Chapter 7: Using the Emulation Analyzer
Qualifying Trigger and Store Conditions
Description
Bus cycle.
Coprocessor cycle.
DMA cycle (for 80186/8/XL/EA).
DMA I/O port read cycle (for
80186/8/XL/EA).
DMA I/O port write cycle (for
80186/8/XL/EA).
DMA memory read cycle (for
80186/8/XL/EA).
DMA memory write cycle (for
80186/8/XL/EA).
Executed instruction state.
Guarded memory access.
Halt acknowledge cycle.
Interrupt acknowledge cycle.
I/O port read cycle.
I/O port write cycle.
Memory read cycle.
Memory write cycle.
Background monitor cycle.
Opcode fetch.
Processor (not DMA) cycle.
Processor halt acknowledge cycle.
Processor int. acknowledge cycle.
Processor I/O port read cycle.
Processor I/O port write cycle.
Processor memory read cycle.
Processor memory write cycle.
Processor opcode fetch.
Processor read cycle.
Processor write cycle.
Access to ROM cycle.
User (foreground) cycle.
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