Motorola PowerQUICC II MPC8280 Series Reference Manual page 1385

Table 40-1 describes I2MOD bit functions.
Bits Name
0–1 — Reserved and should be cleared.
2 REVD Reverse data. Determines the Rx and Tx character bit order.
0 Normal operation. The msb (bit 0) of a character is transferred first.
1 Reverse data. the lsb (bit 7) of a character is transferred first.
Note: Clearing REVD is strongly recommended to ensure consistent bit ordering across devices.
3 GCD General call disable. Determines whether the receiver acknowledges a general call address.
0 General call address is enabled.
1 General call address is disabled.
4 FLT Clock filter. Determines if the I
0 SCL is not filtered.
1 SCL is filtered by a digital filter.
5–6 PDIV Predivider. Selects the clock division factor before it is input into the I
2
the I C BRG is the BRGCLK generated from the CPM clock; see Section 10.4, "System Clock
Control Register (SCCR)."
00 BRGCLK/32
01 BRGCLK/16
10 BRGCLK/8
11 BRGCLK/4
Note: To both save power and reduce noise susceptibility, select the PDIV with the largest division
factor (slowest clock) that still meets performance requirements.
2
7 EN Enable I
2
0 I C is disabled. The I
2
1 I C is enabled. Do not change other I2MOD bits when EN is set.
40.4.2 I C Address Register (I2ADD)
2
2
The I C address register, shown in Figure 40-7, holds the address for this I
0
Field
Reset
R/W
Addr
Table 40-2 describes I2ADD fields.
Bits Name
0–6 SAD Slave address 0–6. Holds the slave address for the I
7 — Reserved and should be cleared.
MOTOROLA
Freescale Semiconductor, Inc.
I
Table 40-1. I 2MOD Field Descriptions
2
C input clock SCL is filtered to prevent spikes in a noisy environment.
C operation.
2
C is in a reset state and consumes minimal power.
SAD
2
Figure 40-7. I C Address Register (I2ADD)
Table 40-2. I2ADD Field Descriptions
Chapter 40. I
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Description
Undefined
R/W
0x11864
Description
2
C port.
2
C Controller
2
I C Registers
2
C BRG. The clock source for
2
C port.
6 7
—
40-7