Motorola PowerQUICC II MPC8280 Series Reference Manual page 1356

Transparent Channel Operation
• Flexible data buffers
• Automatic SYNC detection on receive
— 16-bit pattern
— 8-bit pattern
— Automatic sync (always synchronized)
— External sync signal support
• CRCs can optionally be transmitted and received
• Reverse data mode
• Another protocol can be performed on the FCC's other half (transmitter or receiver)
during transparent mode
• External BD table
38.2 Transparent Channel Operation
The transparent transmitter and receiver operates in the same way as the HDLC controller
of the FCC (see Chapter 37, "FCC HDLC Controller") except in the following ways:
1. The FPSMR does not affect the transparent controller, only the GFMR does.
2. In Table 37-1 on page 37-4, MFLR, HMASK, RFTHR, and RFCNT must be
cleared for proper operation of the transparent receiver.
3. Transmitter synchronization has to be achieved using CTS before the transmitter
begins sending; see Section 38.3, "Achieving Synchronization in Transparent
Mode."
38.3 Achieving Synchronization in Transparent Mode
Once the FCC transmitter is enabled for transparent operation in the GFMR, the TxBD is
prepared for the FCC, and the transmit FIFO is preloaded by the SDMA channel, transmit
synchronization must be established before data can be sent.
Similarly, once the FCC receiver is enabled for transparent operation in the GFMR and the
RxBD is made empty for the FCC, receive synchronization must occur before data can be
received. The synchronization process gives the user bit-level control of when the
transmission and reception begins. The methods for this are as follows:
• An in-line synchronization pattern
• External synchronization signals
• Automatic sync
38-2
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MPC8280 PowerQUICC II Family Reference Manual
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