Motorola PowerQUICC II MPC8280 Series Reference Manual page 1302

Implementation Example
MPC8280
2M Serial Rate
PHY
Idle cell
ATM cell
Figure 35-11. TC Operation in FCC Internal Rate Mode (Sub Rate Mode)
Operation in byte-aligned mode (TCMODE[xTBA] = 1) is required for T1/E1 mainly. In
this mode, once the TC is enabled, it waits for the first Txsyn pulse to start transmit the first
byte of the first cell. This ensures that subsequent Txsyn pulses are byte-aligned to the cell
boundaries.
35.5 Implementation Example
Figure 35-12 shows the MPC8280 connected to two PHY devices, each containing four T1
framers. The eight T1 bit streams are connected to the eight MPC8280 SI TDMs and routed
via the SI to the eight TC layer blocks. The eight TC layer blocks, each with its own
address, are connected internally to FCC2 via the UTOPIA 8-bit bus. Another ATM stream
is managed by FCC1 via the UTOPIA 16-bit bus connected to a SONET 155-Mbps PHY.
35-16
Freescale Semiconductor, Inc.
1M Sub Rate
Generate Cell Req
1M Cell Sub Rate
UTOPIA
TC
Generate Idle Cells
MPC8280 PowerQUICC II Family Reference Manual
For More Information On This Product,
Go to: www.freescale.com
BRG
CP
cell req
BTM
FCC
(Internal/Sub Rate)
Write to FIFO
ATM Cells Only
ATM Channels
DPR
MOTOROLA