Motorola PowerQUICC II MPC8280 Series Reference Manual page 1010

FCC Timing Control
TCLK
TXD
(Output)
RTS
(Output)
CTS
(Input)
Note:
1. GFMR[CTSS] = 0. CTSP=0 or no CTS lost can occur.
TCLK
TXD
(Output)
RTS
(Output)
CTS
(Input)
Note:
1. GFMR[CTSS] = 1. CTSP=0 or no CTS lost can occur.
If GFMR[CTSS] = 1, all CTS transitions must occur while the
transmit clock is low.
Reception delays are determined by CD as Figure 30-12 shows. If GFMR[CDS] = 0, CD is
sampled on the rising receive clock edge before data is received. If GFMR[CDS] = 1, CD
transitions immediately cause data to be gated into the receiver.
30-20
Freescale Semiconductor, Inc.
First Bit of Frame Data
CTS Sampled Low
First Bit of Frame Data
Figure 30-11. CTS Lost
NOTE
MPC8280 PowerQUICC II Family Reference Manual
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Data Forced High
RTS Forced High
CTS Sampled High
CTS Lost Signaled in BD
Data Forced High
RTS Forced High
CTS Lost Signaled in BD
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