Motorola PowerQUICC II MPC8280 Series Reference Manual page 1004

FCC Parameter RAM
Table 30-5. FCC Parameter RAM Common to All Protocols except ATM (continued)
1
Offset Name Width
0x2C TBPTR Word TxBD pointer. Points either to the next BD that the transmitter transfers data from when it
0x30 RCRC Word Temporary receive CRC
0x34 — Word Reserved
0x38 TCRC Word Temporary transmit CRC
0x3C — Word First word of protocol-specific area
1
Offset from FCC base: 0x8400 (FCC1), 0x8500 (FCC2) and 0x8600 (FCC3); see Section 14.5.2, "Parameter RAM."
30.7.1 FCC Function Code Registers (FCRx)
The function code registers contain the transaction specification associated with SDMA
channel accesses to external memory. Figure 30-8 shows the format of the transmit and
receive function code registers, which reside at TSTATE[0–7] and RSTATE[0–7] in the
FCC parameter RAM (see Table 30-5).
0
Field — FCCP
Figure 30-8. Function Code Register (FCRx)
FCRx fields are described in Table 30-6.
Bits Name
0 — Reserved, should be cleared.
1 FCCP FCC priority. Used in conjunction with PPC_ACR[PRKM] (see section 4.3.2.2) and
LCL_ACR[PRKM] (see section 4.3.2.4) for a low request level.
0 Disables CPM low request level to refer to FCCs and MCCs.
1 Enables CPM low request level to refer to FCCs and MCCs.
2 GBL Global. Indicates whether the memory operation should be snooped.
0 Snooping disabled.
1 Snooping enabled.
3–4 BO Byte ordering. Used to select the byte ordering of the buffer. If BO is modified on-the-fly, it takes effect
at the start of the next frame (Ethernet, HDLC, and transparent) or at the beginning of the next BD.
01 Munged little-endian byte ordering. As data is sent onto the serial line from the data buffer, the
LSB of the buffer double-word contains data to be sent earlier than the MSB of the same buffer
double-word.
10 Motorola byte ordering (normal operation). It is also called big-endian byte ordering. As data is
sent onto the serial line from the data buffer, the MSB of the buffer word contains data to be sent
earlier than the LSB of the same buffer word.
30-14
Freescale Semiconductor, Inc.
is in idle state or to the current BD during frame transmission. After a reset or when the
end of the BD table is reached, the CP sets TBPTR = TBASE. Although the user need
never write to TBPTR in most applications, the user can modify it when the transmitter is
disabled or when no transmit buffer is in use (after a
command is issued and the frame completes transmission).
TRANSMIT
1 2 3
GBL
Table 30-6. FCRx Field Descriptions
MPC8280 PowerQUICC II Family Reference Manual
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Description
STOP TRANSMIT
4 5
BO TC2
Description
or
GRACEFUL STOP
6 7
DTB BDB
MOTOROLA