Motorola PowerQUICC II MPC8280 Series Reference Manual page 1112

Transmission Rate Modes—External, Internal, and Expanded Internal
(CMXUAR)." Note that in slave mode, FTIRRx_PHY0 is used regardless of the slave PHY
address.
Field TRM
Reset
R/W
Address
FCC1: 0x1131C (FTIRR1_PHY0),
FCC1: 0x1131D (FTIRR1_PHY1),
Figure 31-62. FCC Transmit Internal Rate Register (FTIRR)
Table 31-50 describes FTIRRx fields.
Bit Name
0 TRM PHY transmit mode
(TIREM=0) 0 External rate mode.
1 Internal rate mode.
TRM Group transmit mode
(TIREM=1) 0 Group rate timer [x] disabled.
1 Internal rate timer for Group[x] is enabled and division factor is set by Initial Value field.
1–7 Initial Value The initial value of the internal rate timer. A value of 0x7F produces the minimum clock rate
(BRG CLK divided by 128); 0x00 produces the maximum clock rate (BRG CLK divided by 1).
Figure 31-63 shows how transmit clocks are determined.
.
BRG CLK
Figure 31-63. FCC Transmit Internal Rate Clocking
31-98
Freescale Semiconductor, Inc.
0 1
GFEMR[TIREM=0]
FCC1: 0x1131E (FTIRR1_PHY2),
FCC1: 0x1131F (FTIRR1_PHY3),
FCC2: 0x1133C (FTIRR2_PHY0),
FCC2: 0x1133D (FTIRR2_PHY1),
FCC2: 0x1133E (FTIRR2_PHY2),
FCC2: 0x1133F (FTIRR2_PHY3).
Table 31-50. FTIRRx Field Descriptions
PHY#0 Int rate timer
PHY#1 Int rate timer
PHY#2 Int rate timer
PHY#3 Int rate timer
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Initial Value
0000_0000
R/W
GFEMR[TIREM=1]
FCC1: 0x1131C (FTIRR1_GRP0),
FCC1: 0x1131D (FTIRR1_GRP1),
FCC1: 0x1131E (FTIRR1_GRP2),
FCC1: 0x1131F (FTIRR1_GRP3),
FCC2: 0x1133C (FTIRR2_GRP0),
FCC2: 0x1133D (FTIRR2_GRP1),
FCC2: 0x1133E (FTIRR2_GRP2),
FCC2: 0x1133F (FTIRR2_GRP3).
Description
PHY# 0 or GRP#0 Tx Rate
PHY# 1 or GRP#1Tx Rate
PHY# 2 or GRP#2 Tx Rate
PHY# 3 or GRP#3 Tx Rate
7
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