Motorola PowerQUICC II MPC8280 Series Reference Manual page 1166

External AAL1 CES Statistics Tables
32.16 External AAL1 CES Statistics Tables
An AAL1 CES statistics table, shown in Table 32-15, resides in the external memory and
holds AAL1 CES statistics on a per-VC basis. AAL1_Ext_STATT_BASE points to the
base address of these tables. Each AAL1 channel has its own table with a starting address
given by AAL1_Ext_STATT_BASE + ATM_CHANNEL# × 16.
Table 32-15. AAL1 CES External Statistics Table
Offset Name
0x00 Rx_AAL1_LOST
0x02 Rx_AAL1_MISS
0x04 Rx_AAL1_SCE
0x06 Rx_SNP_Error
0x08 Rx_AAL1_SPE
0x0A Rx_ReSYNC
0x0C– —
0x0E
Note that both the internal and the external statistics tables should be cleared by the user.
32.17 CES-Specific Additions to the MCC
Additions to the MCC global parameter RAM and modifications to the channel-specific
CHAMR and INTMASK registers have been implemented to support CES operation. Refer
to Section 29.3.3, "MCC Parameters for AAL1 CES Usage," Section 29.3.3.1.1, "Interrupt
Circular Table Entry and Interrupt Mask (INTMSK) —AAL1 CES," and Section 29.3.1.3,
"Channel Mode Register (CHAMR)—HDLC Mode," for more information.
32.18 Application Considerations
• The buffer size (MCC [MRBLR]) must be a multiple of 8 octets.
• The CAS buffer operates in continuous mode with newer signaling information
continuously overwriting older signaling.
• The CES application does not use super-frame synchronization for the data flow in
ATM-to-TDM and TDM-to-ATM interworking. However, for the signaling flow,
32-46
Freescale Semiconductor, Inc.
Width
Hword 16-bit cyclic counter. Counts the number of AAL1 lost cells events. See
Section 32.6, "3-Step-SN Algorithm."
Hword 16-bit cyclic counter. Counts the number of AAL1 misinserted events. See
Section 32.6, "3-Step-SN Algorithm."
Hword 16-bit cyclic counter. Counts the number of AAL1 sequence errors i.e the
expected SC is not match with the received one (ESC!= RSC). See
Section 32.6, "3-Step-SN Algorithm."
Hword 16-bit cyclic counter. Counts the number of ATM cell that received with
SNP error. (AAL1 PDU Header Error)
Hword 16-bit cyclic counter. Counts the number of structured pointer error events
(i.e parity error, Tag cell or pointer mismatch). See Section 32.7, "Pointer
Verification Mechanism."
Hword 16-bit cyclic counter. Counts the number of AAL1 resynchronized events:
pointer reframes, slip events, two consecutive cells with errors (SNE,
SCE, Tag...), and two consecutive pointers with errors (parity error or
pointer mismatch).
Word Reserved, should be cleared during initialization.
MPC8280 PowerQUICC II Family Reference Manual
For More Information On This Product,
Go to: www.freescale.com
Description
MOTOROLA