Motorola PowerQUICC II MPC8280 Series Reference Manual page 1425

Clear. To cause a bit or bit field to register a value of zero. The opposite of
Context synchronization. An operation that ensures that all instructions in
Copy-back. An operation in which modified data in a cache block is copied
Critical-data first. An aspect of burst accesses that allow the requested data
D
Denormalized number. A nonzero floating-point number whose exponent
Direct-mapped cache. A cache in which each main memory address can
Direct-store. Interface available on processors that implement the PowerPC
E
Effective address (EA). The 32- or 64-bit address specified for a load, store,
Exception. A condition encountered by the processor that requires special,
Exception handler. A software routine that executes when an exception is
MOTOROLA
Freescale Semiconductor, Inc.
'set'.
execution complete past the point where they can produce an
exception, that all instructions in execution complete in the context
in which they began execution, and that all subsequent instructions
are fetched and executed in the new context. Context
synchronization may result from executing specific instructions
(such as isync or rfi) or when certain events occur (such as an
exception).
back to memory.
(typically a word or double word) in a cache block to be transferred
first.
has a reserved value, usually the format's minimum, and whose
explicit or implicit leading significand bit is zero.
appear in only one location within the cache. Operates more quickly
when the memory request is a cache hit.
architecture only to support direct-store devices from the POWER
architecture. When the T bit of a segment descriptor is set, the
descriptor defines the region of memory that will be a direct-store
segment. Note that this facility is being phased out of the architecture
and will not likely be supported in future devices. Therefore,
software should not depend on it and new software should not use it.
or an instruction fetch. This address is then submitted to the MMU
for translation to either a physical memory address or an I/O address.
supervisor-level processing.
taken. Normally, the exception handler corrects the condition that
Glossary of Terms and Abbreviations
For More Information On This Product,
Go to: www.freescale.com
Glossary-3