Motorola PowerQUICC II MPC8280 Series Reference Manual page 1396

Port Registers
41.2 Port Registers
Each port has four memory-mapped, read/write, 32-bit control registers.
41.2.1 Port Open-Drain Registers (PODRA–PODRD)
The port open-drain register (PODR), shown in Figure 41-1, indicates a normal or
wired-OR configuration of the port pins.
0 1 2
1 1 1
Field OD0 OD1 OD2
Reset
R/W
Addr 0x10D0C (PODRA), 0x10D2C (PODRB), 0x10D4C (PODRC), 0x10D6C (PODRD)
16 17 18
Field OD16 OD17 OD18 OD19 OD20 OD21 OD22 OD23 OD24 OD25 OD26 OD27 OD28 OD29 OD30 OD31
Reset
R/W
Addr 0x10D0E (PODRA), 0x10D2E (PODRB), 0x10D4E (PODRC), 0x10D6E (PODRD)
1
These bits are valid for PODRA and PODRC only
Figure 41-1. Port Open-Drain Registers (PODRA–PODRD)
Table 41-1 describes PODR fields.
Bits Name
0–31 ODx Open-drain configuration. Determines whether the corresponding pin is actively driven as an output
or is an open-drain driver. Note that bits OD0–OD3 are valid for PODRA and PODRC only.
0 The I/O pin is actively driven as an output.
1 The I/O pin is an open-drain driver. As an output, the pin is driven active-low, otherwise it is
three-stated.
41.2.2 Port Data Registers (PDATA–PDATD)
A read of a port data register (PDATx), shown in Figure 41-2, returns the data at the pin,
independent of whether the pin is defined as an input or output. This allows detection of
output conflicts at the pin by comparing the written data with the data on the pin.
A write to the PDATx is latched and if the equivalent PDIR bit is configured as an output,
the value latched for that bit is driven onto its respective pin. PDATx can be read or written
at any time and is not initialized.
41-2
Freescale Semiconductor, Inc.
3 4 5 6
1
OD3 OD4 OD5 OD6 OD7 OD8 OD9 OD10 OD11 OD12 OD13 OD14 OD15
0000_0000_0000_0000
19 20 21 22
0000_0000_0000_0000
Table 41-1. PODRx Field Descriptions
MPC8280 PowerQUICC II Family Reference Manual
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7 8 9 10 11
R/W
23 24 25 26 27
R/W
Description
12 13 14 15
28 29 30 31
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