Motorola PowerQUICC II MPC8280 Series Reference Manual page 1252

IMA Programming Model
Table 34-18 describes the ITINTSTAT bit fields.
Bits Name
0-3 — Reserved, initialize to zero.
4 PTQO Persistent transmit queue overflow. Set when a transmit queue overflow occurs for two cells in
a row. Further transmit queue overflow events are masked when this bit is set, in order to avoid
a 'flood' of interrupts. This bit can be used to distinguish a temporary overflow condition (which
could be caused by a rate differential between the TRL and non-TRL link which was out of
compensatable range), or a persistent overflow condition (which could be caused by a more
permanent condition, such as a failure of this link's PHY device).
Initialize to zero at link startup.
5 TQO Transmit queue overflow. Set when a transmit queue overflow occurs; cleared when a cell is
successfully transmitted. As this bit is set or cleared on a cell-by-cell basis, it may no longer be
set when software reads it if the overflow condition was only temporary. PTQO should be used
instead to distinguish between persistent or temporary underrun conditions.
6 PTQU Persistent transmit queue underrun. Set when a transmit queue underrun occurs for two cells
in a row. Further transmit queue underrun events are masked when this bit is set, in order to
avoid a 'flood' of interrupts. This bit can be used to distinguish a temporary underrun condition
(which could be caused by a rate differential between the TRL and non-TRL link which was out
of compensatable range), or a persistent underrun condition (which could be caused by a more
permanent condition, such as a TRL failure).
Initialize to zero at link startup.
7 TQU Transmit queue underrun. Set when a transmit queue underrun occurs; cleared when a cell is
successfully transmitted. As this bit is set or cleared on a cell-by-cell basis, it may no longer be
set when software reads it if the underrun condition was only temporary. PTQU should be used
instead to distinguish between persistent or temporary underrun conditions.
Initialize to zero at link startup.
34.4.5.2 IMA Link Receive Table Entry
Offset Name
0x00 ILRCNTL
0x02 ILRSTATE
0x04 ILID
0x05 RMCTR
0x06 LRIFSN
0x07 DFC
34-42
Freescale Semiconductor, Inc.
Table 34-18. ITINTSTAT Field Descriptions
Table 34-19. IMA Link Receive Table Entry
Width
Hword IMA link receive control parameters.
Hword IMA link receive state. Microcode-managed parameter. Initialize to
0x0040 at link startup.
Byte IMA link ID. Formatted per the Cell ID and Link ID field of an ICP cell.
Bit 0: 1 (indicating ICP cell)
Bits 1-2: Program to zero
Bits 3-7: Program to validated LID for this link
[Note: This value is only used by microcode to validate incoming ICP
cells for this link, it is not used to determine round-robin transmission
order. That function is performed by the group order table.]
Byte Receive M counter. Microcode-managed parameter.
Byte Receive IFSN counter. Microcode-managed parameter.
Byte Number of frames to discard on a this link until it is caught up with the
other links in this group (long propagation delay). Microcode-managed
parameter.
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